{"id":812727,"url":"http://patchwork.ozlabs.org/api/patches/812727/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1505205657-18012-2-git-send-email-geert+renesas@glider.be/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505205657-18012-2-git-send-email-geert+renesas@glider.be>","list_archive_url":null,"date":"2017-09-12T08:40:54","name":"[v2,resend,1/4] sh: sh7722: Remove nonexistent GPIO_PTQ7 to fix pinctrl registration","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2af7966a4f957f1ad0707fb98c17b75dfa9281bd","submitter":{"id":63808,"url":"http://patchwork.ozlabs.org/api/people/63808/?format=json","name":"Geert Uytterhoeven","email":"geert+renesas@glider.be"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1505205657-18012-2-git-send-email-geert+renesas@glider.be/mbox/","series":[{"id":2634,"url":"http://patchwork.ozlabs.org/api/series/2634/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=2634","date":"2017-09-12T08:40:55","name":"sh: sh7722/sh7757i/sh7264/sh7269: Fix pinctrl registration","version":2,"mbox":"http://patchwork.ozlabs.org/series/2634/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812727/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812727/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xryvs5WBHz9s81\n\tfor ;\n\tTue, 12 Sep 2017 18:42:01 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751354AbdILIl7 (ORCPT );\n\tTue, 12 Sep 2017 04:41:59 -0400","from xavier.telenet-ops.be ([195.130.132.52]:51532 \"EHLO\n\txavier.telenet-ops.be\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751332AbdILIlD (ORCPT\n\t); Tue, 12 Sep 2017 04:41:03 -0400","from ayla.of.borg ([84.195.106.246])\n\tby xavier.telenet-ops.be with bizsmtp\n\tid 8Ygz1w00g5JzmfG01YgzyB; Tue, 12 Sep 2017 10:41:02 +0200","from ramsan.of.borg ([192.168.97.29] helo=ramsan)\n\tby ayla.of.borg with esmtp (Exim 4.86_2)\n\t(envelope-from )\n\tid 1drgkZ-0003Xv-DR; Tue, 12 Sep 2017 10:40:55 +0200","from geert by ramsan with local (Exim 4.86_2)\n\t(envelope-from )\n\tid 1drgkd-0004hJ-Ln; Tue, 12 Sep 2017 10:40:59 +0200"],"From":"Geert Uytterhoeven ","To":"Andrew Morton ","Cc":"Yoshinori Sato ,\n\tRich Felker , Magnus Damm ,\n\tLaurent Pinchart ,\n\tYoshihiro Shimoda ,\n\tlinux-sh@vger.kernel.org, linux-renesas-soc@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tGeert Uytterhoeven ","Subject":"[PATCH v2 resend 1/4] sh: sh7722: Remove nonexistent GPIO_PTQ7 to\n\tfix pinctrl registration","Date":"Tue, 12 Sep 2017 10:40:54 +0200","Message-Id":"<1505205657-18012-2-git-send-email-geert+renesas@glider.be>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1505205657-18012-1-git-send-email-geert+renesas@glider.be>","References":"<1505205657-18012-1-git-send-email-geert+renesas@glider.be>","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"},"content":"On sh7722/Migo-R, pinctrl registration fails with:\n\n sh-pfc pfc-sh7722: pin 0 already registered\n sh-pfc pfc-sh7722: error during pin registration\n sh-pfc pfc-sh7722: could not register: -22\n sh-pfc: probe of pfc-sh7722 failed with error -22\n\npinmux_pins[] is initialized through PINMUX_GPIO(), using designated\narray initializers, where the GPIO_* enums serve as indices.\nAs GPIO_PTQ7 is defined in the enum, but never used, pinmux_pins[]\ncontains a (zero-filled) hole. Hence this entry is treated as pin zero,\nwhich was registered before, and pinctrl registration fails.\n\nAccording to the datasheet, port PTQ7 does not exist. Hence remove\nGPIO_PTQ7 from the enum to fix this.\n\nFixes: 8d7b5b0af7e070b9 (\"sh: Add sh7722 pinmux code\")\nReported-by: Magnus Damm \nSigned-off-by: Geert Uytterhoeven \nReviewed-by: Laurent Pinchart \nTested-by: Jacopo Mondi \n---\nTested on sh7722/Migo-R.\n\nv2:\n - Add Reviewed-by, Tested-by.\n---\n arch/sh/include/cpu-sh4/cpu/sh7722.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)","diff":"diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h\nindex 3bb74e534d0f8ca4..78961ab78a5a9c83 100644\n--- a/arch/sh/include/cpu-sh4/cpu/sh7722.h\n+++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h\n@@ -67,7 +67,7 @@ enum {\n \tGPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,\n \n \t/* PTQ */\n-\tGPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,\n+\tGPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,\n \tGPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,\n \n \t/* PTR */\n","prefixes":["v2","resend","1/4"]}