{"id":812720,"url":"http://patchwork.ozlabs.org/api/patches/812720/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/1505205277-26276-2-git-send-email-charles.baylis@linaro.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505205277-26276-2-git-send-email-charles.baylis@linaro.org>","list_archive_url":null,"date":"2017-09-12T08:34:35","name":"[1/3,ARM] Add bus_width_bits to tune_params","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1a03f2bab5536b7c8ac0d9975c22e6c6d6ef5d69","submitter":{"id":35578,"url":"http://patchwork.ozlabs.org/api/people/35578/?format=json","name":"Charles Baylis","email":"charles.baylis@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/1505205277-26276-2-git-send-email-charles.baylis@linaro.org/mbox/","series":[{"id":2631,"url":"http://patchwork.ozlabs.org/api/series/2631/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=2631","date":"2017-09-12T08:34:34","name":"Addressing mode costs v3","version":1,"mbox":"http://patchwork.ozlabs.org/series/2631/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812720/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812720/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references; bh=//UwRE2ND77guwTYUG3tcO2LhAn9wAAvlnwex+hmMq4=;\n\tb=P4yNHi/PbaYRxka9M5vZJyeJvXDHlxBVi61ENLZ/ex2H8So/dmvgvcmRcEoxkyraJy\n\tDWD2PFuijLayohqfVsehXwMDujjPSbKhk4CpGIFqy/uqKDQe+zznCwA6u2D5S2vApFaC\n\tYON74OIKzRCy5FOAmre4L88BVLiJ/fkFya30DcVIlmdVnUDJD1nUbB95AxguR80wv18h\n\teK3H3+74ugYGhI+xtcPNaZA6IW2kkIZP0XY6PJAmoODT5t4OlNNVHw6dCXUcbK6zoBv5\n\tqNARLzAOLt5TQZZXS8CKi5gFFf3Slt4270322EEDUKTQ47p3WiLnvwcnN/BVsTA3mb6w\n\tce3A==","X-Gm-Message-State":"AHPjjUgnNJv9rvuttJZ5sbNV9KAFbdDdP9RlEKmNIM4i7FPctDRfLYeR\tPTpY4xrRSoKpfdtW","X-Google-Smtp-Source":"ADKCNb4kfqZB7oSnkZeZ0u9hutwxZtsy+HyAnl1sYdbjc9N+C/ZO4l6NA8xM8hv9qmqELAoxMtGSyw==","X-Received":"by 10.223.170.202 with SMTP id\n\ti10mr11500880wrc.232.1505205293363;\n\tTue, 12 Sep 2017 01:34:53 -0700 (PDT)","From":"charles.baylis@linaro.org","To":"rearnsha@arm.com, Ramana.Radhakrishnan@arm.com, pinskia@gmail.com,\n\tkyrylo.tkachov@arm.com","Cc":"gcc-patches@gcc.gnu.org","Subject":"[PATCH 1/3] [ARM] Add bus_width_bits to tune_params","Date":"Tue, 12 Sep 2017 09:34:35 +0100","Message-Id":"<1505205277-26276-2-git-send-email-charles.baylis@linaro.org>","In-Reply-To":"<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>","References":"<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>","X-IsSubscribed":"yes"},"content":"From: Charles Baylis \n\nAdd bus widths. These use the approximation that v7 and later cores have\n64bit data bus width, and earlier cores have 32 bit bus width, with the\nexception of v7m.\n\n Charles Baylis \n\n\t* config/arm/arm-protos.h (struct tune_params): New field\n\tbus_width.\n\t* config/arm/arm.c (arm_slowmul_tune): Initialise bus_width field.\n\t(arm_fastmul_tune): Likewise.\n\t(arm_strongarm_tune): Likewise.\n\t(arm_xscale_tune): Likewise.\n\t(arm_9e_tune): Likewise.\n\t(arm_marvell_pj4_tune): Likewise.\n\t(arm_v6t2_tune): Likewise.\n\t(arm_cortex_tune): Likewise.\n\t(arm_cortex_a8_tune): Likewise.\n\t(arm_cortex_a7_tune): Likewise.\n\t(arm_cortex_a15_tune): Likewise.\n\t(arm_cortex_a35_tune): Likewise.\n\t(arm_cortex_a53_tune): Likewise.\n\t(arm_cortex_a57_tune): Likewise.\n\t(arm_exynosm1_tune): Likewise.\n\t(arm_xgene1_tune): Likewise.\n\t(arm_cortex_a5_tune): Likewise.\n\t(arm_cortex_a9_tune): Likewise.\n\t(arm_cortex_a12_tune): Likewise.\n\t(arm_cortex_a73_tune): Likewise.\n\t(arm_v7m_tune): Likewise.\n\t(arm_cortex_m7_tune): Likewise.\n\t(arm_v6m_tune): Likewise.\n\t(arm_fa726te_tune): Likewise.\n\nChange-Id: I613e876db93ffd6f8c1e72ba483be2efc0b56d66\n---\n gcc/config/arm/arm-protos.h | 2 ++\n gcc/config/arm/arm.c | 24 ++++++++++++++++++++++++\n 2 files changed, 26 insertions(+)","diff":"diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h\nindex 4538078..47a85cc 100644\n--- a/gcc/config/arm/arm-protos.h\n+++ b/gcc/config/arm/arm-protos.h\n@@ -278,6 +278,8 @@ struct tune_params\n int max_insns_inline_memset;\n /* Issue rate of the processor. */\n unsigned int issue_rate;\n+ /* Bus width (bits). */\n+ unsigned int bus_width;\n /* Explicit prefetch data. */\n struct\n {\ndiff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\nindex bca8a34..32001e5 100644\n--- a/gcc/config/arm/arm.c\n+++ b/gcc/config/arm/arm.c\n@@ -1761,6 +1761,7 @@ const struct tune_params arm_slowmul_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1783,6 +1784,7 @@ const struct tune_params arm_fastmul_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1808,6 +1810,7 @@ const struct tune_params arm_strongarm_tune =\n 3,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1830,6 +1833,7 @@ const struct tune_params arm_xscale_tune =\n 3,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1852,6 +1856,7 @@ const struct tune_params arm_9e_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1874,6 +1879,7 @@ const struct tune_params arm_marvell_pj4_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1896,6 +1902,7 @@ const struct tune_params arm_v6t2_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1920,6 +1927,7 @@ const struct tune_params arm_cortex_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1942,6 +1950,7 @@ const struct tune_params arm_cortex_a8_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1964,6 +1973,7 @@ const struct tune_params arm_cortex_a7_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1986,6 +1996,7 @@ const struct tune_params arm_cortex_a15_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 3,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2008,6 +2019,7 @@ const struct tune_params arm_cortex_a35_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2030,6 +2042,7 @@ const struct tune_params arm_cortex_a53_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2052,6 +2065,7 @@ const struct tune_params arm_cortex_a57_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 3,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2074,6 +2088,7 @@ const struct tune_params arm_exynosm1_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 3,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2096,6 +2111,7 @@ const struct tune_params arm_xgene1_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 32,\t\t\t\t\t\t/* Memset max inline. */\n 4,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2121,6 +2137,7 @@ const struct tune_params arm_cortex_a5_tune =\n 1,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2143,6 +2160,7 @@ const struct tune_params arm_cortex_a9_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_BENEFICIAL(4,32,32),\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2165,6 +2183,7 @@ const struct tune_params arm_cortex_a12_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2187,6 +2206,7 @@ const struct tune_params arm_cortex_a73_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2216,6 +2236,7 @@ const struct tune_params arm_v7m_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2240,6 +2261,7 @@ const struct tune_params arm_cortex_m7_tune =\n 1,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2265,6 +2287,7 @@ const struct tune_params arm_v6m_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2287,6 +2310,7 @@ const struct tune_params arm_fa726te_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n","prefixes":["1/3","ARM"]}