{"id":812489,"url":"http://patchwork.ozlabs.org/api/patches/812489/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-22-clg@kaod.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170911171235.29331-22-clg@kaod.org>","list_archive_url":null,"date":"2017-09-11T17:12:35","name":"[RFC,v2,21/21] spapr: activate XIVE exploitation mode","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9d2e2c399bff67e109342beaa0021d6989c38f07","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/people/68548/?format=json","name":"Cédric Le Goater","email":"clg@kaod.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-22-clg@kaod.org/mbox/","series":[{"id":2526,"url":"http://patchwork.ozlabs.org/api/series/2526/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2526","date":"2017-09-11T17:12:14","name":"Guest exploitation of the XIVE interrupt controller (POWER9)","version":2,"mbox":"http://patchwork.ozlabs.org/series/2526/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812489/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812489/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrZsM5PQlz9s81\n\tfor ;\n\tTue, 12 Sep 2017 03:38:31 +1000 (AEST)","from localhost ([::1]:59410 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drSfF-0006BQ-Qp\n\tfor incoming@patchwork.ozlabs.org; Mon, 11 Sep 2017 13:38:29 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:35984)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drSIw-0002Uw-A2\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:15:30 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drSIr-00054a-BI\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:15:26 -0400","from 7.mo2.mail-out.ovh.net ([188.165.48.182]:34120)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1drSIr-00054K-1Y\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:15:21 -0400","from player770.ha.ovh.net (b6.ovh.net [213.186.33.56])\n\tby mo2.mail-out.ovh.net (Postfix) with ESMTP id 14321AB263\n\tfor ; Mon, 11 Sep 2017 19:15:20 +0200 (CEST)","from zorba.kaod.org.com (LFbn-1-2231-173.w90-76.abo.wanadoo.fr\n\t[90.76.52.173]) (Authenticated sender: clg@kaod.org)\n\tby player770.ha.ovh.net (Postfix) with ESMTPSA id D9A563C0073;\n\tMon, 11 Sep 2017 19:15:12 +0200 (CEST)"],"From":"=?utf-8?q?C=C3=A9dric_Le_Goater?= ","To":"qemu-ppc@nongnu.org, qemu-devel@nongnu.org,\n\tDavid Gibson ,\n\tBenjamin Herrenschmidt ,\n\tAlexey Kardashevskiy , Alexander Graf ","Date":"Mon, 11 Sep 2017 19:12:35 +0200","Message-Id":"<20170911171235.29331-22-clg@kaod.org>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170911171235.29331-1-clg@kaod.org>","References":"<20170911171235.29331-1-clg@kaod.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","X-Ovh-Tracer-Id":"14170576229094099795","X-VR-SPAMSTATE":"OK","X-VR-SPAMSCORE":"-100","X-VR-SPAMCAUSE":"gggruggvucftvghtrhhoucdtuddrfeelledrgedtgdduudeiucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"188.165.48.182","Subject":"[Qemu-devel] [RFC PATCH v2 21/21] spapr: activate XIVE exploitation\n\tmode","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?C=C3=A9dric_Le_Goater?= ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"A couple of adjustments need to be done to activate XIVE exploitation\nmode. First, the hypervisor should advertise support for both models\nXIVE legacy and XIVE exploitation in \"ibm,arch-vec-5-platform-support\".\n\nThe sPAPR machine starts with the XICS interrupt model (the default\nbehavior could be changed later on for POWER9) and, depending on the\nguest capabilities, the XIVE exploitation mode is negotiated during\nCAS. A reset is then performed to rebuild the device tree with new\nXIVE properties under the \"interrupt-controller\" node.\n\nFinally, the MMIO regions for the ESB and TIMA should be mapped at\nreset time and post_load when XIVE exploitation mode is on.\n\nSigned-off-by: Cédric Le Goater \n---\n hw/ppc/spapr.c | 33 ++++++++++++++++++++++++++++++---\n hw/ppc/spapr_hcall.c | 6 ++++++\n 2 files changed, 36 insertions(+), 3 deletions(-)","diff":"diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c\nindex d8b25be70cd8..aaf1be7a50fe 100644\n--- a/hw/ppc/spapr.c\n+++ b/hw/ppc/spapr.c\n@@ -942,7 +942,8 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)\n /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features\n * that the guest may request and thus the valid values for bytes 24..26 of\n * option vector 5: */\n-static void spapr_dt_ov5_platform_support(void *fdt, int chosen)\n+static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr,\n+ void *fdt, int chosen)\n {\n PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);\n \n@@ -961,6 +962,13 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen)\n } else {\n val[3] = 0x00; /* Hash */\n }\n+\n+ /* TODO: introduce a kvmppc_has_cap_xive() ? Works with\n+ * irqchip=off for now\n+ */\n+ if (spapr->xive) {\n+ val[1] = 0x80; /* OV5_XIVE_BOTH */\n+ }\n } else {\n if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) {\n /* V3 MMU supports both hash and radix (with dynamic switching) */\n@@ -969,6 +977,9 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen)\n /* Otherwise we can only do hash */\n val[3] = 0x00;\n }\n+ if (spapr->xive) {\n+ val[1] = 0x80; /* OV5_XIVE_BOTH */\n+ }\n }\n _FDT(fdt_setprop(fdt, chosen, \"ibm,arch-vec-5-platform-support\",\n val, sizeof(val)));\n@@ -1027,7 +1038,7 @@ static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)\n _FDT(fdt_setprop_string(fdt, chosen, \"linux,stdout-path\", stdout_path));\n }\n \n- spapr_dt_ov5_platform_support(fdt, chosen);\n+ spapr_dt_ov5_platform_support(spapr, fdt, chosen);\n \n g_free(stdout_path);\n g_free(bootlist);\n@@ -1106,7 +1117,13 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr,\n _FDT(fdt_setprop_cell(fdt, 0, \"#size-cells\", 2));\n \n /* /interrupt controller */\n- spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);\n+ if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {\n+ spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);\n+ } else {\n+ /* populate device tree for XIVE */ ;\n+ spapr_xive_populate(spapr->xive, fdt, PHANDLE_XICP);\n+ spapr_xive_mmio_map(spapr->xive);\n+ }\n \n ret = spapr_populate_memory(spapr, fdt);\n if (ret < 0) {\n@@ -1552,6 +1569,10 @@ static int spapr_post_load(void *opaque, int version_id)\n }\n }\n \n+ if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {\n+ spapr_xive_mmio_map(spapr->xive);\n+ }\n+\n return err;\n }\n \n@@ -2332,6 +2353,7 @@ static void ppc_spapr_init(MachineState *machine)\n XICS_IRQS_SPAPR + xics_max_server_number(),\n xics_max_server_number(),\n &error_fatal);\n+ spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);\n }\n }\n \n@@ -3463,6 +3485,11 @@ static qemu_irq spapr_qirq_get(XICSFabric *dev, int irq)\n return NULL;\n }\n \n+ /* use XIVE qirqs when XIVE exploitation mode is on */\n+ if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {\n+ return spapr->xive->qirqs[irq - spapr->ics->offset];\n+ }\n+\n return spapr->ics->qirqs[irq - spapr->ics->offset];\n }\n \ndiff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c\nindex 92f1e21358b8..ba00b8d3fdd6 100644\n--- a/hw/ppc/spapr_hcall.c\n+++ b/hw/ppc/spapr_hcall.c\n@@ -1613,6 +1613,12 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,\n (spapr_h_cas_compose_response(spapr, args[1], args[2],\n ov5_updates) != 0);\n }\n+\n+ /* We need to rebuild the device tree for XIVE, generate a reset */\n+ if (!spapr->cas_reboot) {\n+ spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT);\n+ }\n+\n spapr_ovec_cleanup(ov5_updates);\n \n if (spapr->cas_reboot) {\n","prefixes":["RFC","v2","21/21"]}