{"id":812472,"url":"http://patchwork.ozlabs.org/api/patches/812472/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-12-clg@kaod.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170911171235.29331-12-clg@kaod.org>","list_archive_url":null,"date":"2017-09-11T17:12:25","name":"[RFC,v2,11/21] ppc/xive: push the EQ data in OS event queue","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a48706a94298563de620dde9f847db412c445441","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/people/68548/?format=json","name":"Cédric Le Goater","email":"clg@kaod.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-12-clg@kaod.org/mbox/","series":[{"id":2526,"url":"http://patchwork.ozlabs.org/api/series/2526/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2526","date":"2017-09-11T17:12:14","name":"Guest exploitation of the XIVE interrupt controller (POWER9)","version":2,"mbox":"http://patchwork.ozlabs.org/series/2526/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812472/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812472/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrZZv0HT1z9s83\n\tfor ;\n\tTue, 12 Sep 2017 03:25:59 +1000 (AEST)","from localhost ([::1]:59335 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drST7-0002gO-3J\n\tfor incoming@patchwork.ozlabs.org; Mon, 11 Sep 2017 13:25:57 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:35308)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drSHl-0001JE-CQ\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:18 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drSHh-0004Qk-8d\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:13 -0400","from 8.mo2.mail-out.ovh.net ([188.165.52.147]:43955)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1drSHh-0004QQ-2A\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:09 -0400","from player770.ha.ovh.net (b6.ovh.net [213.186.33.56])\n\tby mo2.mail-out.ovh.net (Postfix) with ESMTP id 1C75BAB215\n\tfor ; Mon, 11 Sep 2017 19:14:08 +0200 (CEST)","from zorba.kaod.org.com (LFbn-1-2231-173.w90-76.abo.wanadoo.fr\n\t[90.76.52.173]) (Authenticated sender: clg@kaod.org)\n\tby player770.ha.ovh.net (Postfix) with ESMTPSA id E113D3C0072;\n\tMon, 11 Sep 2017 19:14:00 +0200 (CEST)"],"From":"=?utf-8?q?C=C3=A9dric_Le_Goater?= ","To":"qemu-ppc@nongnu.org, qemu-devel@nongnu.org,\n\tDavid Gibson ,\n\tBenjamin Herrenschmidt ,\n\tAlexey Kardashevskiy , Alexander Graf ","Date":"Mon, 11 Sep 2017 19:12:25 +0200","Message-Id":"<20170911171235.29331-12-clg@kaod.org>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170911171235.29331-1-clg@kaod.org>","References":"<20170911171235.29331-1-clg@kaod.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","X-Ovh-Tracer-Id":"14150310029844908883","X-VR-SPAMSTATE":"OK","X-VR-SPAMSCORE":"-100","X-VR-SPAMCAUSE":"gggruggvucftvghtrhhoucdtuddrfeelledrgedtgdduudehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"188.165.52.147","Subject":"[Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in OS\n\tevent queue","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?C=C3=A9dric_Le_Goater?= ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"If a triggered event is let through, the Event Queue data defined in\nthe associated IVE is pushed in the in-memory event queue. The latter\nis a circular buffer provided by the OS using the H_INT_SET_QUEUE_CONFIG\nhcall, one per target and priority couple. It is composed of Event\nQueue entries which are 4 bytes long, the first bit being a\n'generation' bit and the 31 following bits the EQ Data field.\n\nThe EQ Data field provides a way to set an invariant logical event\nsource number for an IRQ. It is set with the H_INT_SET_SOURCE_CONFIG\nhcall.\n\nNotification of the CPU will be done in the following patch.\n\nSigned-off-by: Cédric Le Goater \n---\n hw/intc/spapr_xive.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 67 insertions(+)","diff":"diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\nindex 557a7e2535b5..4bc61cfda67a 100644\n--- a/hw/intc/spapr_xive.c\n+++ b/hw/intc/spapr_xive.c\n@@ -175,9 +175,76 @@ static const MemoryRegionOps spapr_xive_tm_ops = {\n },\n };\n \n+static void spapr_xive_eq_push(XiveEQ *eq, uint32_t data)\n+{\n+ uint64_t qaddr_base = (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3;\n+ uint32_t qsize = GETFIELD(EQ_W0_QSIZE, eq->w0);\n+ uint32_t qindex = GETFIELD(EQ_W1_PAGE_OFF, eq->w1);\n+ uint32_t qgen = GETFIELD(EQ_W1_GENERATION, eq->w1);\n+\n+ uint64_t qaddr = qaddr_base + (qindex << 2);\n+ uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));\n+ uint32_t qentries = 1 << (qsize + 10);\n+\n+ if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: failed to write EQ data @0x%\"\n+ HWADDR_PRIx \"\\n\", __func__, qaddr);\n+ return;\n+ }\n+\n+ qindex = (qindex + 1) % qentries;\n+ if (qindex == 0) {\n+ qgen ^= 1;\n+ eq->w1 = SETFIELD(EQ_W1_GENERATION, eq->w1, qgen);\n+ }\n+ eq->w1 = SETFIELD(EQ_W1_PAGE_OFF, eq->w1, qindex);\n+}\n+\n static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n {\n+ XiveIVE *ive;\n+ XiveEQ *eq;\n+ uint32_t eq_idx;\n+ uint32_t priority;\n+\n+ ive = spapr_xive_get_ive(xive, srcno);\n+ if (!ive || !(ive->w & IVE_VALID)) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: invalid LISN %d\\n\", srcno);\n+ return;\n+ }\n+\n+ if (ive->w & IVE_MASKED) {\n+ return;\n+ }\n+\n+ /* Find our XiveEQ */\n+ eq_idx = GETFIELD(IVE_EQ_INDEX, ive->w);\n+ eq = spapr_xive_get_eq(xive, eq_idx);\n+ if (!eq) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: No EQ for LISN %d\\n\", srcno);\n+ return;\n+ }\n+\n+ if (eq->w0 & EQ_W0_ENQUEUE) {\n+ spapr_xive_eq_push(eq, GETFIELD(IVE_EQ_DATA, ive->w));\n+ } else {\n+ qemu_log_mask(LOG_UNIMP, \"XIVE: !ENQUEUE not implemented\\n\");\n+ }\n+\n+ if (!(eq->w0 & EQ_W0_UCOND_NOTIFY)) {\n+ qemu_log_mask(LOG_UNIMP, \"XIVE: !UCOND_NOTIFY not implemented\\n\");\n+ }\n+\n+ if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {\n+ priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);\n \n+ /* The EQ is masked. Can this happen ? */\n+ if (priority == 0xff) {\n+ return;\n+ }\n+ } else {\n+ qemu_log_mask(LOG_UNIMP, \"XIVE: w7 format1 not implemented\\n\");\n+ }\n }\n \n /*\n","prefixes":["RFC","v2","11/21"]}