{"id":812460,"url":"http://patchwork.ozlabs.org/api/patches/812460/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-7-clg@kaod.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170911171235.29331-7-clg@kaod.org>","list_archive_url":null,"date":"2017-09-11T17:12:20","name":"[RFC,v2,06/21] ppc/xive: introduce handlers for interrupt sources","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0544ba48bd596ddc25409c7f9e40a0a0954fc6b4","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/people/68548/?format=json","name":"Cédric Le Goater","email":"clg@kaod.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-7-clg@kaod.org/mbox/","series":[{"id":2526,"url":"http://patchwork.ozlabs.org/api/series/2526/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2526","date":"2017-09-11T17:12:14","name":"Guest exploitation of the XIVE interrupt controller (POWER9)","version":2,"mbox":"http://patchwork.ozlabs.org/series/2526/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812460/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812460/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrZP26brDz9s83\n\tfor ;\n\tTue, 12 Sep 2017 03:17:26 +1000 (AEST)","from localhost ([::1]:59280 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drSKq-0003Xj-UA\n\tfor incoming@patchwork.ozlabs.org; Mon, 11 Sep 2017 13:17:24 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:34922)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drSHD-0000mk-Ah\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:13:43 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drSH7-0003z8-M0\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:13:39 -0400","from 3.mo2.mail-out.ovh.net ([46.105.58.226]:40795)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1drSH7-0003yW-DC\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:13:33 -0400","from player770.ha.ovh.net (b6.ovh.net [213.186.33.56])\n\tby mo2.mail-out.ovh.net (Postfix) with ESMTP id 2337AAB138\n\tfor ; Mon, 11 Sep 2017 19:13:32 +0200 (CEST)","from zorba.kaod.org.com (LFbn-1-2231-173.w90-76.abo.wanadoo.fr\n\t[90.76.52.173]) (Authenticated sender: clg@kaod.org)\n\tby player770.ha.ovh.net (Postfix) with ESMTPSA id B54D03C006E;\n\tMon, 11 Sep 2017 19:13:24 +0200 (CEST)"],"From":"=?utf-8?q?C=C3=A9dric_Le_Goater?= ","To":"qemu-ppc@nongnu.org, qemu-devel@nongnu.org,\n\tDavid Gibson ,\n\tBenjamin Herrenschmidt ,\n\tAlexey Kardashevskiy , Alexander Graf ","Date":"Mon, 11 Sep 2017 19:12:20 +0200","Message-Id":"<20170911171235.29331-7-clg@kaod.org>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170911171235.29331-1-clg@kaod.org>","References":"<20170911171235.29331-1-clg@kaod.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","X-Ovh-Tracer-Id":"14140176933383408467","X-VR-SPAMSTATE":"OK","X-VR-SPAMSCORE":"-100","X-VR-SPAMCAUSE":"gggruggvucftvghtrhhoucdtuddrfeelledrgedtgdduudehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"46.105.58.226","Subject":"[Qemu-devel] [RFC PATCH v2 06/21] ppc/xive: introduce handlers for\n\tinterrupt sources","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?C=C3=A9dric_Le_Goater?= ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"These are very similar to the XICS handlers in a simpler form. They\nmake use of the ICSIRQState array of the XICS interrupt source to\ndifferentiate the MSI from the LSI interrupts. The spapr_xive_irq()\nroutine in charge of triggering the CPU interrupt line will be filled\nlater on.\n\nThe next patch will introduce the MMIO handlers to interact with XIVE\ninterrupt sources.\n\nSigned-off-by: Cédric Le Goater \n---\n hw/intc/spapr_xive.c | 46 +++++++++++++++++++++++++++++++++++++++++++++\n include/hw/ppc/spapr_xive.h | 1 +\n 2 files changed, 47 insertions(+)","diff":"diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\nindex 52c32f588d6d..1ed7b6a286e9 100644\n--- a/hw/intc/spapr_xive.c\n+++ b/hw/intc/spapr_xive.c\n@@ -27,6 +27,50 @@\n \n #include \"xive-internal.h\"\n \n+static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n+{\n+\n+}\n+\n+/*\n+ * XIVE Interrupt Source\n+ */\n+static void spapr_xive_source_set_irq_msi(sPAPRXive *xive, int srcno, int val)\n+{\n+ if (val) {\n+ spapr_xive_irq(xive, srcno);\n+ }\n+}\n+\n+static void spapr_xive_source_set_irq_lsi(sPAPRXive *xive, int srcno, int val)\n+{\n+ ICSIRQState *irq = &xive->ics->irqs[srcno];\n+\n+ if (val) {\n+ irq->status |= XICS_STATUS_ASSERTED;\n+ } else {\n+ irq->status &= ~XICS_STATUS_ASSERTED;\n+ }\n+\n+ if (irq->status & XICS_STATUS_ASSERTED\n+ && !(irq->status & XICS_STATUS_SENT)) {\n+ irq->status |= XICS_STATUS_SENT;\n+ spapr_xive_irq(xive, srcno);\n+ }\n+}\n+\n+static void spapr_xive_source_set_irq(void *opaque, int srcno, int val)\n+{\n+ sPAPRXive *xive = SPAPR_XIVE(opaque);\n+ ICSIRQState *irq = &xive->ics->irqs[srcno];\n+\n+ if (irq->flags & XICS_FLAGS_IRQ_LSI) {\n+ spapr_xive_source_set_irq_lsi(xive, srcno, val);\n+ } else {\n+ spapr_xive_source_set_irq_msi(xive, srcno, val);\n+ }\n+}\n+\n /*\n * Main XIVE object\n */\n@@ -80,6 +124,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)\n }\n \n xive->ics = ICS_BASE(obj);\n+ xive->qirqs = qemu_allocate_irqs(spapr_xive_source_set_irq, xive,\n+ xive->nr_irqs);\n \n /* Allocate the last IRQ numbers for the IPIs */\n for (i = xive->nr_irqs - xive->nr_targets; i < xive->nr_irqs; i++) {\ndiff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h\nindex 29112589b37f..eab92c4c1bb8 100644\n--- a/include/hw/ppc/spapr_xive.h\n+++ b/include/hw/ppc/spapr_xive.h\n@@ -38,6 +38,7 @@ struct sPAPRXive {\n \n /* IRQ */\n ICSState *ics; /* XICS source inherited from the SPAPR machine */\n+ qemu_irq *qirqs;\n \n /* XIVE internal tables */\n uint8_t *sbe;\n","prefixes":["RFC","v2","06/21"]}