{"id":812291,"url":"http://patchwork.ozlabs.org/api/patches/812291/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/patch/1505122921-5534-10-git-send-email-bmeng.cn@gmail.com/","project":{"id":3,"url":"http://patchwork.ozlabs.org/api/projects/3/?format=json","name":"Linux MTD development","link_name":"linux-mtd","list_id":"linux-mtd.lists.infradead.org","list_email":"linux-mtd@lists.infradead.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505122921-5534-10-git-send-email-bmeng.cn@gmail.com>","list_archive_url":null,"date":"2017-09-11T09:41:59","name":"[v2,09/10] spi-nor: intel-spi: Rename swseq to swseq_reg in 'struct intel_spi'","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"6d14cc18e10eea1406f2df6553b0378870d99fc1","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/people/64981/?format=json","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"delegate":{"id":63396,"url":"http://patchwork.ozlabs.org/api/users/63396/?format=json","username":"cpitchen","first_name":"Cyrille","last_name":"Pitchen","email":"cyrille.pitchen@atmel.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-mtd/patch/1505122921-5534-10-git-send-email-bmeng.cn@gmail.com/mbox/","series":[{"id":2464,"url":"http://patchwork.ozlabs.org/api/series/2464/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/list/?series=2464","date":"2017-09-11T09:41:50","name":"spi-nor: intel-spi: Various fixes and enhancements","version":2,"mbox":"http://patchwork.ozlabs.org/series/2464/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812291/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812291/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"The ispi->swseq is used for register access. Let's rename it to\nswseq_reg to better describe its usage.\n\nSigned-off-by: Bin Meng \nAcked-by: Mika Westerberg \n---\n\nChanges in v2: None\n\n drivers/mtd/spi-nor/intel-spi.c | 16 ++++++++--------\n 1 file changed, 8 insertions(+), 8 deletions(-)","diff":"diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c\nindex 91ceef7..5e7a389 100644\n--- a/drivers/mtd/spi-nor/intel-spi.c\n+++ b/drivers/mtd/spi-nor/intel-spi.c\n@@ -126,7 +126,7 @@\n * @pr_num: Maximum number of protected range registers\n * @writeable: Is the chip writeable\n * @locked: Is SPI setting locked\n- * @swseq: Use SW sequencer in register reads/writes\n+ * @swseq_reg: Use SW sequencer in register reads/writes\n * @erase_64k: 64k erase supported\n * @opcodes: Opcodes which are supported. This are programmed by BIOS\n * before it locks down the controller.\n@@ -143,7 +143,7 @@ struct intel_spi {\n \tsize_t pr_num;\n \tbool writeable;\n \tbool locked;\n-\tbool swseq;\n+\tbool swseq_reg;\n \tbool erase_64k;\n \tu8 opcodes[8];\n \tu8 preopcodes[2];\n@@ -224,7 +224,7 @@ static void intel_spi_dump_regs(struct intel_spi *ispi)\n \t}\n \n \tdev_dbg(ispi->dev, \"Using %cW sequencer for register access\\n\",\n-\t\tispi->swseq ? 'S' : 'H');\n+\t\tispi->swseq_reg ? 'S' : 'H');\n }\n \n /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */\n@@ -297,7 +297,7 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t\tispi->pregs = ispi->base + BYT_PR;\n \t\tispi->nregions = BYT_FREG_NUM;\n \t\tispi->pr_num = BYT_PR_NUM;\n-\t\tispi->swseq = true;\n+\t\tispi->swseq_reg = true;\n \n \t\tif (writeable) {\n \t\t\t/* Disable write protection */\n@@ -318,7 +318,7 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t\tispi->pregs = ispi->base + LPT_PR;\n \t\tispi->nregions = LPT_FREG_NUM;\n \t\tispi->pr_num = LPT_PR_NUM;\n-\t\tispi->swseq = true;\n+\t\tispi->swseq_reg = true;\n \t\tbreak;\n \n \tcase INTEL_SPI_BXT:\n@@ -343,7 +343,7 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t * sequencer. All other operations are supposed to be carried out\n \t * using software sequencer.\n \t */\n-\tif (ispi->swseq) {\n+\tif (ispi->swseq_reg) {\n \t\t/* Disable #SMI generation from SW sequencer */\n \t\tval = readl(ispi->sregs + SSFSTS_CTL);\n \t\tval &= ~SSFSTS_CTL_FSMIE;\n@@ -493,7 +493,7 @@ static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)\n \t/* Address of the first chip */\n \twritel(0, ispi->base + FADDR);\n \n-\tif (ispi->swseq)\n+\tif (ispi->swseq_reg)\n \t\tret = intel_spi_sw_cycle(ispi, opcode, len,\n \t\t\t\t\t OPTYPE_READ_NO_ADDR);\n \telse\n@@ -529,7 +529,7 @@ static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)\n \tif (ret)\n \t\treturn ret;\n \n-\tif (ispi->swseq)\n+\tif (ispi->swseq_reg)\n \t\treturn intel_spi_sw_cycle(ispi, opcode, len,\n \t\t\t\t\t OPTYPE_WRITE_NO_ADDR);\n \treturn intel_spi_hw_cycle(ispi, opcode, len);\n","prefixes":["v2","09/10"]}