{"id":812286,"url":"http://patchwork.ozlabs.org/api/patches/812286/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/patch/1505122921-5534-5-git-send-email-bmeng.cn@gmail.com/","project":{"id":3,"url":"http://patchwork.ozlabs.org/api/projects/3/?format=json","name":"Linux MTD development","link_name":"linux-mtd","list_id":"linux-mtd.lists.infradead.org","list_email":"linux-mtd@lists.infradead.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505122921-5534-5-git-send-email-bmeng.cn@gmail.com>","list_archive_url":null,"date":"2017-09-11T09:41:54","name":"[v2,04/10] spi-nor: intel-spi: Check transfer length in the HW/SW cycle","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"3c8cf2f4b09f3a45395c243ab9408b8f12b87a53","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/people/64981/?format=json","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"delegate":{"id":63396,"url":"http://patchwork.ozlabs.org/api/users/63396/?format=json","username":"cpitchen","first_name":"Cyrille","last_name":"Pitchen","email":"cyrille.pitchen@atmel.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-mtd/patch/1505122921-5534-5-git-send-email-bmeng.cn@gmail.com/mbox/","series":[{"id":2464,"url":"http://patchwork.ozlabs.org/api/series/2464/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/list/?series=2464","date":"2017-09-11T09:41:50","name":"spi-nor: intel-spi: Various fixes and enhancements","version":2,"mbox":"http://patchwork.ozlabs.org/series/2464/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812286/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812286/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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\n\tMon, 11 Sep 2017 02:37:46 -0700 (PDT)","From":"Bin Meng ","To":"Mika Westerberg ,\n\tCyrille Pitchen ,\n\tMarek Vasut ,\n\tBoris Brezillon ,\n\tBrian Norris ,\n\tRichard Weinberger ,\n\tDavid Woodhouse , \n\tlinux-mtd ,\n\tlinux-kernel ","Subject":"[PATCH v2 04/10] spi-nor: intel-spi: Check transfer length in the\n\tHW/SW cycle","Date":"Mon, 11 Sep 2017 02:41:54 -0700","Message-Id":"<1505122921-5534-5-git-send-email-bmeng.cn@gmail.com>","X-Mailer":"git-send-email 1.7.9.5","In-Reply-To":"<1505122921-5534-1-git-send-email-bmeng.cn@gmail.com>","References":"<1505122921-5534-1-git-send-email-bmeng.cn@gmail.com>","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170911_023807_777170_5021F303 ","X-CRM114-Status":"GOOD ( 13.07 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2607:f8b0:4001:c06:0:0:0:243 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (bmeng.cn[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Stefan Roese ","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"Intel SPI controller only has a 64 bytes FIFO. This adds a sanity\ncheck before triggering any HW/SW sequencer work.\n\nAdditionally for the SW sequencer, if given data length is zero,\nwe should not mark the 'Data Cycle' bit.\n\nSigned-off-by: Bin Meng \nAcked-by: Mika Westerberg \n---\n\nChanges in v2: None\n\n drivers/mtd/spi-nor/intel-spi.c | 12 ++++++++++--\n 1 file changed, 10 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c\nindex 263c6ab..c4a9de6 100644\n--- a/drivers/mtd/spi-nor/intel-spi.c\n+++ b/drivers/mtd/spi-nor/intel-spi.c\n@@ -399,6 +399,9 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n \t\treturn -EINVAL;\n \t}\n \n+\tif (len > INTEL_SPI_FIFO_SZ)\n+\t\treturn -EINVAL;\n+\n \tval |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;\n \tval |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;\n \tval |= HSFSTS_CTL_FGO;\n@@ -419,14 +422,19 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n \n static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n {\n-\tu32 val, status;\n+\tu32 val = 0, status;\n \tint ret;\n \n \tret = intel_spi_opcode_index(ispi, opcode);\n \tif (ret < 0)\n \t\treturn ret;\n \n-\tval = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;\n+\tif (len > INTEL_SPI_FIFO_SZ)\n+\t\treturn -EINVAL;\n+\n+\t/* Only mark 'Data Cycle' bit when there is data to be transferred */\n+\tif (len > 0)\n+\t\tval = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;\n \tval |= ret << SSFSTS_CTL_COP_SHIFT;\n \tval |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;\n \tval |= SSFSTS_CTL_SCGO;\n","prefixes":["v2","04/10"]}