{"id":812282,"url":"http://patchwork.ozlabs.org/api/patches/812282/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/patch/1505122921-5534-2-git-send-email-bmeng.cn@gmail.com/","project":{"id":3,"url":"http://patchwork.ozlabs.org/api/projects/3/?format=json","name":"Linux MTD development","link_name":"linux-mtd","list_id":"linux-mtd.lists.infradead.org","list_email":"linux-mtd@lists.infradead.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505122921-5534-2-git-send-email-bmeng.cn@gmail.com>","list_archive_url":null,"date":"2017-09-11T09:41:51","name":"[v2,01/10] spi-nor: intel-spi: Fix number of protected range registers for BYT/LPT","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"455984302a25329ed24dbad91fdbe330d932c530","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/people/64981/?format=json","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"delegate":{"id":63396,"url":"http://patchwork.ozlabs.org/api/users/63396/?format=json","username":"cpitchen","first_name":"Cyrille","last_name":"Pitchen","email":"cyrille.pitchen@atmel.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-mtd/patch/1505122921-5534-2-git-send-email-bmeng.cn@gmail.com/mbox/","series":[{"id":2464,"url":"http://patchwork.ozlabs.org/api/series/2464/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/list/?series=2464","date":"2017-09-11T09:41:50","name":"spi-nor: intel-spi: Various fixes and enhancements","version":2,"mbox":"http://patchwork.ozlabs.org/series/2464/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812282/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812282/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"The number of protected range registers is not the same on BYT/LPT/\nBXT. GPR0 only exists on Apollo Lake and its offset is reserved on\nother platforms.\n\nSigned-off-by: Bin Meng \nAcked-by: Mika Westerberg \n---\n\nChanges in v2: None\n\n drivers/mtd/spi-nor/intel-spi.c | 16 +++++++++++-----\n 1 file changed, 11 insertions(+), 5 deletions(-)","diff":"diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c\nindex 8a596bf..e5b52e8 100644\n--- a/drivers/mtd/spi-nor/intel-spi.c\n+++ b/drivers/mtd/spi-nor/intel-spi.c\n@@ -67,8 +67,6 @@\n #define PR_LIMIT_MASK\t\t\t(0x3fff << PR_LIMIT_SHIFT)\n #define PR_RPE\t\t\t\tBIT(15)\n #define PR_BASE_MASK\t\t\t0x3fff\n-/* Last PR is GPR0 */\n-#define PR_NUM\t\t\t\t(5 + 1)\n \n /* Offsets are from @ispi->sregs */\n #define SSFSTS_CTL\t\t\t0x00\n@@ -96,14 +94,17 @@\n #define BYT_BCR\t\t\t\t0xfc\n #define BYT_BCR_WPD\t\t\tBIT(0)\n #define BYT_FREG_NUM\t\t\t5\n+#define BYT_PR_NUM\t\t\t5\n \n #define LPT_PR\t\t\t\t0x74\n #define LPT_SSFSTS_CTL\t\t\t0x90\n #define LPT_FREG_NUM\t\t\t5\n+#define LPT_PR_NUM\t\t\t5\n \n #define BXT_PR\t\t\t\t0x84\n #define BXT_SSFSTS_CTL\t\t\t0xa0\n #define BXT_FREG_NUM\t\t\t12\n+#define BXT_PR_NUM\t\t\t6\n \n #define INTEL_SPI_TIMEOUT\t\t5000 /* ms */\n #define INTEL_SPI_FIFO_SZ\t\t64\n@@ -117,6 +118,7 @@\n * @pregs: Start of protection registers\n * @sregs: Start of software sequencer registers\n * @nregions: Maximum number of regions\n+ * @pr_num: Maximum number of protected range registers\n * @writeable: Is the chip writeable\n * @swseq: Use SW sequencer in register reads/writes\n * @erase_64k: 64k erase supported\n@@ -132,6 +134,7 @@ struct intel_spi {\n \tvoid __iomem *pregs;\n \tvoid __iomem *sregs;\n \tsize_t nregions;\n+\tsize_t pr_num;\n \tbool writeable;\n \tbool swseq;\n \tbool erase_64k;\n@@ -167,7 +170,7 @@ static void intel_spi_dump_regs(struct intel_spi *ispi)\n \tfor (i = 0; i < ispi->nregions; i++)\n \t\tdev_dbg(ispi->dev, \"FREG(%d)=0x%08x\\n\", i,\n \t\t\treadl(ispi->base + FREG(i)));\n-\tfor (i = 0; i < PR_NUM; i++)\n+\tfor (i = 0; i < ispi->pr_num; i++)\n \t\tdev_dbg(ispi->dev, \"PR(%d)=0x%08x\\n\", i,\n \t\t\treadl(ispi->pregs + PR(i)));\n \n@@ -182,7 +185,7 @@ static void intel_spi_dump_regs(struct intel_spi *ispi)\n \t\tdev_dbg(ispi->dev, \"BCR=0x%08x\\n\", readl(ispi->base + BYT_BCR));\n \n \tdev_dbg(ispi->dev, \"Protected regions:\\n\");\n-\tfor (i = 0; i < PR_NUM; i++) {\n+\tfor (i = 0; i < ispi->pr_num; i++) {\n \t\tu32 base, limit;\n \n \t\tvalue = readl(ispi->pregs + PR(i));\n@@ -286,6 +289,7 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t\tispi->sregs = ispi->base + BYT_SSFSTS_CTL;\n \t\tispi->pregs = ispi->base + BYT_PR;\n \t\tispi->nregions = BYT_FREG_NUM;\n+\t\tispi->pr_num = BYT_PR_NUM;\n \n \t\tif (writeable) {\n \t\t\t/* Disable write protection */\n@@ -305,12 +309,14 @@ static int intel_spi_init(struct intel_spi *ispi)\n \t\tispi->sregs = ispi->base + LPT_SSFSTS_CTL;\n \t\tispi->pregs = ispi->base + LPT_PR;\n \t\tispi->nregions = LPT_FREG_NUM;\n+\t\tispi->pr_num = LPT_PR_NUM;\n \t\tbreak;\n \n \tcase INTEL_SPI_BXT:\n \t\tispi->sregs = ispi->base + BXT_SSFSTS_CTL;\n \t\tispi->pregs = ispi->base + BXT_PR;\n \t\tispi->nregions = BXT_FREG_NUM;\n+\t\tispi->pr_num = BXT_PR_NUM;\n \t\tispi->erase_64k = true;\n \t\tbreak;\n \n@@ -652,7 +658,7 @@ static bool intel_spi_is_protected(const struct intel_spi *ispi,\n {\n \tint i;\n \n-\tfor (i = 0; i < PR_NUM; i++) {\n+\tfor (i = 0; i < ispi->pr_num; i++) {\n \t\tu32 pr_base, pr_limit, pr_value;\n \n \t\tpr_value = readl(ispi->pregs + PR(i));\n","prefixes":["v2","01/10"]}