{"id":812254,"url":"http://patchwork.ozlabs.org/api/patches/812254/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/patch/1505118939-32030-1-git-send-email-maddy@linux.vnet.ibm.com/","project":{"id":44,"url":"http://patchwork.ozlabs.org/api/projects/44/?format=json","name":"skiboot firmware development","link_name":"skiboot","list_id":"skiboot.lists.ozlabs.org","list_email":"skiboot@lists.ozlabs.org","web_url":"http://github.com/open-power/skiboot","scm_url":"http://github.com/open-power/skiboot","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505118939-32030-1-git-send-email-maddy@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-09-11T08:35:39","name":"[v2] skiboot/skiboot.tcl: Add imc device nodes to skiboot.tcl","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"3ebd0cf0dc830f5e393db82e66ab768ab5c9c181","submitter":{"id":33703,"url":"http://patchwork.ozlabs.org/api/people/33703/?format=json","name":"maddy","email":"maddy@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/skiboot/patch/1505118939-32030-1-git-send-email-maddy@linux.vnet.ibm.com/mbox/","series":[{"id":2457,"url":"http://patchwork.ozlabs.org/api/series/2457/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/list/?series=2457","date":"2017-09-11T08:35:39","name":"[v2] skiboot/skiboot.tcl: Add imc device nodes to skiboot.tcl","version":2,"mbox":"http://patchwork.ozlabs.org/series/2457/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812254/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812254/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrLrr1JVzz9s83\n\tfor ;\n\tMon, 11 Sep 2017 18:37:16 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xrLrq6JCYzDrny\n\tfor ;\n\tMon, 11 Sep 2017 18:37:15 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xrLrg6kBZzDrZf\n\tfor ; Mon, 11 Sep 2017 18:37:07 +1000 (AEST)","from pps.filterd (m0098394.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8B8ZNuA069465\n\tfor ; Mon, 11 Sep 2017 04:37:05 -0400","from e23smtp06.au.ibm.com (e23smtp06.au.ibm.com [202.81.31.148])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cweu4vnpw-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Mon, 11 Sep 2017 04:37:05 -0400","from localhost\n\tby e23smtp06.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"},"content":"Add In-Memory Collection counter dummy nodes to the skiboot.tcl\nto aid code testing in mambo for both OPAL and Kernel side enablement.\n\nSigned-off-by: Madhavan Srinivasan \n---\nChangelog v1:\n- Included more code patch to ve covered inmambo before checking for\n mambo quirk\n- Updated UAV vector to fake it incase of mambo\n\n external/mambo/skiboot.tcl | 82 ++++++++++++++++++++++++++++++++++++++++++++++\n hw/imc.c | 40 ++++++++++++++++++++--\n 2 files changed, 120 insertions(+), 2 deletions(-)","diff":"diff --git a/external/mambo/skiboot.tcl b/external/mambo/skiboot.tcl\nindex 46d8569018be..ad10355a8551 100644\n--- a/external/mambo/skiboot.tcl\n+++ b/external/mambo/skiboot.tcl\n@@ -325,6 +325,88 @@ for { set c 0 } { $c < $mconf(cpus) } { incr c } {\n mysim of addprop $cpu_node array \"ibm,ppc-interrupt-server#s\" irqreg\n }\n \n+#Add In-Memory Collection Counter nodes\n+if { $default_config == \"P9\" } {\n+ #Add the base node \"imc-counters\"\n+ set imc_c [mysim of addchild $root_node \"imc-counters\" \"\"]\n+ mysim of addprop $imc_c string \"compatible\" \"ibm,opal-in-memory-counters\"\n+ mysim of addprop $imc_c int \"#address-cells\" 1\n+ mysim of addprop $imc_c int \"#size-cells\" 1\n+ mysim of addprop $imc_c int \"version-id\" 1\n+\n+ #Add a common mcs event node\n+ set mcs_et [mysim of addchild $imc_c \"nest-mcs-events\" \"\"]\n+ mysim of addprop $mcs_et int \"#address-cells\" 1\n+ mysim of addprop $mcs_et int \"#size-cells\" 1\n+\n+ #Add a event\n+ set et [mysim of addchild $mcs_et event [format %x 0]]\n+ mysim of addprop $et string \"event-name\" \"64B_RD_OR_WR_DISP_PORT01\"\n+ mysim of addprop $et string \"unit\" \"MiB/s\"\n+ mysim of addprop $et string \"scale\" \"4\"\n+ mysim of addprop $et int \"reg\" 0\n+\n+ #Add a event\n+ set et [mysim of addchild $mcs_et event [format %x 1]]\n+ mysim of addprop $et string \"event-name\" \"64B_WR_DISP_PORT01\"\n+ mysim of addprop $et string \"unit\" \"MiB/s\"\n+ mysim of addprop $et int \"reg\" 40\n+\n+ #Add a event\n+ set et [mysim of addchild $mcs_et event [format %x 2]]\n+ mysim of addprop $et string \"event-name\" \"64B_RD_DISP_PORT01\"\n+ mysim of addprop $et string \"scale\" \"100\"\n+ mysim of addprop $et int \"reg\" 64\n+\n+ #Add a event\n+ set et [mysim of addchild $mcs_et event [format %x 3]]\n+ mysim of addprop $et string \"event-name\" \"64B_XX_DISP_PORT01\"\n+ mysim of addprop $et int \"reg\" 32\n+\n+ #Add a mcs device node\n+ set mcs_01 [mysim of addchild $imc_c \"mcs01\" \"\"]\n+ mysim of addprop $mcs_01 string \"compatible\" \"ibm,imc-counters\"\n+ mysim of addprop $mcs_01 string \"events-prefix\" \"PM_MCS01_\"\n+ mysim of addprop $mcs_01 int \"reg\" 65536\n+ mysim of addprop $mcs_01 int \"size\" 262144\n+ mysim of addprop $mcs_01 int \"offset\" 1572864\n+ mysim of addprop $mcs_01 int \"events\" $mcs_et\n+ mysim of addprop $mcs_01 int \"type\" 16\n+ mysim of addprop $mcs_01 string \"unit\" \"KiB/s\"\n+ mysim of addprop $mcs_01 string \"scale\" \"8\"\n+\n+ #Add a common core event node\n+ set ct_et [mysim of addchild $imc_c \"core-thread-events\" \"\"]\n+ mysim of addprop $ct_et int \"#address-cells\" 1\n+ mysim of addprop $ct_et int \"#size-cells\" 1\n+\n+ #Add a event\n+ set cet [mysim of addchild $ct_et event [format %x 200]]\n+ mysim of addprop $cet string \"event-name\" \"0THRD_NON_IDLE_PCYC\"\n+ mysim of addprop $cet string \"desc\" \"The number of processor cycles when all threads are idle\"\n+ mysim of addprop $cet int \"reg\" 200\n+\n+ #Add a core device node\n+ set core [mysim of addchild $imc_c \"core\" \"\"]\n+ mysim of addprop $core string \"compatible\" \"ibm,imc-counters\"\n+ mysim of addprop $core string \"events-prefix\" \"CPM_\"\n+ mysim of addprop $core int \"reg\" 24\n+ mysim of addprop $core int \"size\" 8192\n+ mysim of addprop $core string \"scale\" \"512\"\n+ mysim of addprop $core int \"events\" $ct_et\n+ mysim of addprop $core int \"type\" 4\n+\n+ #Add a thread device node\n+ set thread [mysim of addchild $imc_c \"thread\" \"\"]\n+ mysim of addprop $thread string \"compatible\" \"ibm,imc-counters\"\n+ mysim of addprop $thread string \"events-prefix\" \"CPM_\"\n+ mysim of addprop $thread int \"reg\" 24\n+ mysim of addprop $thread int \"size\" 8192\n+ mysim of addprop $thread string \"scale\" \"512\"\n+ mysim of addprop $thread int \"events\" $ct_et\n+ mysim of addprop $thread int \"type\" 1\n+}\n+\n mconfig enable_stb SKIBOOT_ENABLE_MAMBO_STB 0\n \n if { [info exists env(SKIBOOT_ENABLE_MAMBO_STB)] } {\ndiff --git a/hw/imc.c b/hw/imc.c\nindex ccf3973c4752..60fc39d6b761 100644\n--- a/hw/imc.c\n+++ b/hw/imc.c\n@@ -310,9 +310,14 @@ static void disable_unavailable_units(struct dt_node *dev)\n \tcb = get_imc_cb(this_cpu()->chip_id);\n \tif (cb)\n \t\tavl_vec = be64_to_cpu(cb->imc_chip_avl_vector);\n-\telse\n+\telse {\n \t\tavl_vec = 0; /* Remove only nest imc device nodes */\n \n+\t\t/* Incase of mambo, just fake it */\n+\t\tif (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)\n+\t\t\tavl_vec = (0xffULL) << 56;\n+\t}\n+\n \tfor (i = 0; i < MAX_NEST_UNITS; i++) {\n \t\tif (!(PPC_BITMASK(i, i) & avl_vec)) {\n \t\t\t/* Check if the device node exists */\n@@ -365,6 +370,9 @@ void imc_catalog_preload(void)\n \tint ret = OPAL_SUCCESS;\n \tcompress_buf_size = MAX_COMPRESSED_IMC_DTB_SIZE;\n \n+\tif (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)\n+\t\treturn;\n+\n \t/* Enable only for power 9 */\n \tif (proc_gen != proc_gen_p9)\n \t\treturn;\n@@ -421,11 +429,20 @@ static void imc_dt_update_nest_node(struct dt_node *dev)\n */\n void imc_init(void)\n {\n-\tvoid *decompress_buf;\n+\tvoid *decompress_buf = NULL;\n \tuint32_t pvr = (mfspr(SPR_PVR) & ~(0xf000));\n \tstruct dt_node *dev;\n \tint ret;\n \n+\tif (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) {\n+\t\tdev = dt_find_compatible_node(dt_root, NULL,\n+\t\t\t\t\t\"ibm,opal-in-memory-counters\");\n+\t\tif (!dev)\n+\t\t\treturn;\n+\n+\t\tgoto imc_mambo;\n+\t}\n+\n \t/* Enable only for power 9 */\n \tif (proc_gen != proc_gen_p9)\n \t\treturn;\n@@ -481,6 +498,7 @@ void imc_init(void)\n \t\tgoto err;\n \t}\n \n+imc_mambo:\n \t/* Check and remove unsupported imc device types */\n \tcheck_imc_device_type(dev);\n \n@@ -496,6 +514,9 @@ void imc_init(void)\n \t/* Update the base_addr and chip-id for nest nodes */\n \timc_dt_update_nest_node(dev);\n \n+\tif (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)\n+\t\treturn;\n+\n \t/*\n \t * If the dt_attach_root() fails, \"imc-counters\" node will not be\n \t * seen in the device-tree and hence OS should not make any\n@@ -541,6 +562,9 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu\n \t\tphys_core_id = cpu_get_core_index(c);\n \t\tport_id = phys_core_id % 4;\n \n+\t\tif (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)\n+\t\t\treturn OPAL_SUCCESS;\n+\n \t\t/*\n \t\t * Core IMC hardware mandate initing of three scoms\n \t\t * to enbale or disable of the Core IMC engine.\n@@ -605,6 +629,9 @@ static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir)\n \t\t/* Set the run command */\n \t\top = NEST_IMC_ENABLE;\n \n+\t\tif (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)\n+\t\t\treturn OPAL_SUCCESS;\n+\n \t\t/* Write the command to the control block now */\n \t\tcb->imc_chip_command = cpu_to_be64(op);\n \n@@ -617,6 +644,9 @@ static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir)\n \t\tphys_core_id = cpu_get_core_index(c);\n \t\tport_id = phys_core_id % 4;\n \n+\t\tif (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)\n+\t\t\treturn OPAL_SUCCESS;\n+\n \t\t/*\n \t\t * Enables the core imc engine by appropriately setting\n \t\t * bits 4-9 of the HTM_MODE scom port. No initialization\n@@ -659,6 +689,9 @@ static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir)\n \t\t/* Set the run command */\n \t\top = NEST_IMC_DISABLE;\n \n+\t\tif (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)\n+\t\t\treturn OPAL_SUCCESS;\n+\n \t\t/* Write the command to the control block */\n \t\tcb->imc_chip_command = cpu_to_be64(op);\n \n@@ -672,6 +705,9 @@ static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir)\n \t\tphys_core_id = cpu_get_core_index(c);\n \t\tport_id = phys_core_id % 4;\n \n+\t\tif (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)\n+\t\t\treturn OPAL_SUCCESS;\n+\n \t\t/*\n \t\t * Disables the core imc engine by clearing\n \t\t * bits 4-9 of the HTM_MODE scom port.\n","prefixes":["v2"]}