{"id":812218,"url":"http://patchwork.ozlabs.org/api/patches/812218/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/patch/20170911022241.11603-5-afaerber@suse.de/","project":{"id":19,"url":"http://patchwork.ozlabs.org/api/projects/19/?format=json","name":"Linux IMX development","link_name":"linux-imx","list_id":"linux-imx-kernel.lists.patchwork.ozlabs.org","list_email":"linux-imx-kernel@lists.patchwork.ozlabs.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170911022241.11603-5-afaerber@suse.de>","list_archive_url":null,"date":"2017-09-11T02:22:41","name":"[4/4] arm64: dts: actions: Add S700 and CubieBoard7","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"521d75fd784a05f58434203e3edb0b7717a4750d","submitter":{"id":9542,"url":"http://patchwork.ozlabs.org/api/people/9542/?format=json","name":"Andreas Färber","email":"afaerber@suse.de"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-imx/patch/20170911022241.11603-5-afaerber@suse.de/mbox/","series":[{"id":2431,"url":"http://patchwork.ozlabs.org/api/series/2431/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/list/?series=2431","date":"2017-09-11T02:22:40","name":"arm64: Add initial Actions Semi S700 and CubieBoard7 support","version":1,"mbox":"http://patchwork.ozlabs.org/series/2431/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812218/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812218/checks/","tags":{},"related":[],"headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) 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(Exim 4.87 #1 (Red Hat Linux))\n\tid 1drENV-0006S1-GY for linux-arm-kernel@lists.infradead.org;\n\tMon, 11 Sep 2017 02:23:18 +0000","from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254])\n\tby mx1.suse.de (Postfix) with ESMTP id 08EA3AC12;\n\tMon, 11 Sep 2017 02:22:51 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; 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","X-CRM114-CacheID":"sfid-20170910_192314_073286_FFAB4792 ","X-CRM114-Status":"GOOD (  14.06  )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-4.2 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [195.135.220.15 listed in list.dnswl.org]\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"Mark Rutland <mark.rutland@arm.com>, support@cubietech.com,\n\t=?utf-8?b?5byg5aSp55uK?= <tyzhang@actions-semi.com>, =?utf-8?b?5qKF5Yip?=\n\t<harrymei@actions-semi.com>, Catalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will.deacon@arm.com>, linux-kernel@vger.kernel.org,\n\tThomas Liau <thomas.liau@actions-semi.com>, devicetree@vger.kernel.org,\n\tRob Herring <robh+dt@kernel.org>, =?utf-8?b?5byg5Lic6aOO?=\n\t<zhangdf@actions-semi.com>, =?utf-8?b?5YiY54Kc?=\n\t<liuwei@actions-semi.com>, =?utf-8?q?Andreas_F=C3=A4rber?=\n\t<afaerber@suse.de>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"Add Device Trees for S700 SoC and Cubietech CubieBoard7.\n\nSigned-off-by: Andreas Färber <afaerber@suse.de>\n---\n arch/arm64/boot/dts/actions/Makefile             |   2 +\n arch/arm64/boot/dts/actions/s700-cubieboard7.dts |  47 +++++++\n arch/arm64/boot/dts/actions/s700.dtsi            | 164 +++++++++++++++++++++++\n 3 files changed, 213 insertions(+)\n create mode 100644 arch/arm64/boot/dts/actions/s700-cubieboard7.dts\n create mode 100644 arch/arm64/boot/dts/actions/s700.dtsi","diff":"diff --git a/arch/arm64/boot/dts/actions/Makefile b/arch/arm64/boot/dts/actions/Makefile\nindex 62922d688ce3..cfd7f2679feb 100644\n--- a/arch/arm64/boot/dts/actions/Makefile\n+++ b/arch/arm64/boot/dts/actions/Makefile\n@@ -1,3 +1,5 @@\n+dtb-$(CONFIG_ARCH_ACTIONS) += s700-cubieboard7.dtb\n+\n dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb\n \n always\t\t:= $(dtb-y)\ndiff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts\nnew file mode 100644\nindex 000000000000..e562f04c2490\n--- /dev/null\n+++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts\n@@ -0,0 +1,47 @@\n+/*\n+ * Copyright (c) 2017 Andreas Färber\n+ *\n+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+ */\n+\n+/dts-v1/;\n+\n+#include \"s700.dtsi\"\n+\n+/ {\n+\tcompatible = \"cubietech,cubieboard7\", \"actions,s700\";\n+\tmodel = \"CubieBoard7\";\n+\n+\taliases {\n+\t\tserial3 = &uart3;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial3:115200n8\";\n+\t};\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x0 0x0 0x0 0x80000000>;\n+\t};\n+\n+\tmemory@1,e0000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x1 0xe0000000 0x0 0x0>;\n+\t};\n+\n+\tuart3_clk: uart3-clk {\n+\t\tcompatible = \"fixed-clock\";\n+\t\tclock-frequency = <921600>;\n+\t\t#clock-cells = <0>;\n+\t};\n+};\n+\n+&timer {\n+\tclocks = <&hosc>;\n+};\n+\n+&uart3 {\n+\tstatus = \"okay\";\n+\tclocks = <&uart3_clk>;\n+};\ndiff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi\nnew file mode 100644\nindex 000000000000..b54df405aaeb\n--- /dev/null\n+++ b/arch/arm64/boot/dts/actions/s700.dtsi\n@@ -0,0 +1,164 @@\n+/*\n+ * Copyright (c) 2017 Andreas Färber\n+ *\n+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+ */\n+\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+/ {\n+\tcompatible = \"actions,s700\";\n+\tinterrupt-parent = <&gic>;\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\tcpus {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n+\t\t\treg = <0x0 0x0>;\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu1: cpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n+\t\t\treg = <0x0 0x1>;\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu2: cpu@2 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n+\t\t\treg = <0x0 0x2>;\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu3: cpu@3 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n+\t\t\treg = <0x0 0x3>;\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\tsecmon@1f000000 {\n+\t\t\treg = <0x0 0x1f000000 0x0 0x1000000>;\n+\t\t\tno-map;\n+\t\t};\n+\t};\n+\n+\tpsci {\n+\t\tcompatible = \"arm,psci-0.2\";\n+\t\tmethod = \"smc\";\n+\t};\n+\n+\tarm-pmu {\n+\t\tcompatible = \"arm,cortex-a53-pmu\";\n+\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tinterrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupts = <GIC_PPI 13\n+\t\t\t(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t     <GIC_PPI 14\n+\t\t\t(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t     <GIC_PPI 11\n+\t\t\t(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t     <GIC_PPI 10\n+\t\t\t(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n+\t};\n+\n+\thosc: hosc {\n+\t\tcompatible = \"fixed-clock\";\n+\t\tclock-frequency = <24000000>;\n+\t\t#clock-cells = <0>;\n+\t};\n+\n+\tsoc {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\tgic: interrupt-controller@e00f1000 {\n+\t\t\tcompatible = \"arm,gic-400\";\n+\t\t\treg = <0x0 0xe00f1000 0x0 0x1000>,\n+\t\t\t      <0x0 0xe00f2000 0x0 0x2000>,\n+\t\t\t      <0x0 0xe00f4000 0x0 0x2000>,\n+\t\t\t      <0x0 0xe00f6000 0x0 0x2000>;\n+\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <3>;\n+\t\t};\n+\n+\t\tuart0: serial@e0120000 {\n+\t\t\tcompatible = \"actions,s900-uart\", \"actions,owl-uart\";\n+\t\t\treg = <0x0 0xe0120000 0x0 0x2000>;\n+\t\t\tinterrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart1: serial@e0122000 {\n+\t\t\tcompatible = \"actions,s900-uart\", \"actions,owl-uart\";\n+\t\t\treg = <0x0 0xe0122000 0x0 0x2000>;\n+\t\t\tinterrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart2: serial@e0124000 {\n+\t\t\tcompatible = \"actions,s900-uart\", \"actions,owl-uart\";\n+\t\t\treg = <0x0 0xe0124000 0x0 0x2000>;\n+\t\t\tinterrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart3: serial@e0126000 {\n+\t\t\tcompatible = \"actions,s900-uart\", \"actions,owl-uart\";\n+\t\t\treg = <0x0 0xe0126000 0x0 0x2000>;\n+\t\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart4: serial@e0128000 {\n+\t\t\tcompatible = \"actions,s900-uart\", \"actions,owl-uart\";\n+\t\t\treg = <0x0 0xe0128000 0x0 0x2000>;\n+\t\t\tinterrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart5: serial@e012a000 {\n+\t\t\tcompatible = \"actions,s900-uart\", \"actions,owl-uart\";\n+\t\t\treg = <0x0 0xe012a000 0x0 0x2000>;\n+\t\t\tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart6: serial@e012c000 {\n+\t\t\tcompatible = \"actions,s900-uart\", \"actions,owl-uart\";\n+\t\t\treg = <0x0 0xe012c000 0x0 0x2000>;\n+\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ttimer: timer@e024c000 {\n+\t\t\tcompatible = \"actions,s700-timer\";\n+\t\t\treg = <0x0 0xe024c000 0x0 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"timer1\";\n+\t\t};\n+\t};\n+};\n","prefixes":["4/4"]}