{"id":812165,"url":"http://patchwork.ozlabs.org/api/patches/812165/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150506107741.19604.8328467942268087647.stgit@frigg.lan/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<150506107741.19604.8328467942268087647.stgit@frigg.lan>","list_archive_url":null,"date":"2017-09-10T16:31:17","name":"[5/7] trace: Add event \"guest_bbl_after\"","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b43456e55ad88e55e7ff96845a06655526e1114c","submitter":{"id":9099,"url":"http://patchwork.ozlabs.org/api/people/9099/?format=json","name":"Lluís Vilanova","email":"vilanova@ac.upc.edu"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150506107741.19604.8328467942268087647.stgit@frigg.lan/mbox/","series":[{"id":2406,"url":"http://patchwork.ozlabs.org/api/series/2406/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2406","date":"2017-09-10T16:11:07","name":"trace: Add guest code events","version":1,"mbox":"http://patchwork.ozlabs.org/series/2406/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812165/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812165/checks/","tags":{},"related":[],"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xqxR74ffCz9ryT\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 11 Sep 2017 02:32:03 +1000 (AEST)","from localhost ([::1]:53589 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dr59N-0001Fm-Q8\n\tfor incoming@patchwork.ozlabs.org; Sun, 10 Sep 2017 12:32:01 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43219)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <vilanova@ac.upc.edu>) id 1dr58r-0001ES-Pm\n\tfor qemu-devel@nongnu.org; Sun, 10 Sep 2017 12:31:31 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <vilanova@ac.upc.edu>) id 1dr58n-00078e-Qq\n\tfor qemu-devel@nongnu.org; Sun, 10 Sep 2017 12:31:29 -0400","from roura.ac.upc.es ([147.83.33.10]:35341)\n\tby eggs.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <vilanova@ac.upc.edu>) id 1dr58n-00078C-CI\n\tfor qemu-devel@nongnu.org; Sun, 10 Sep 2017 12:31:25 -0400","from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91])\n\tby roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v8AGVOxX020554;\n\tSun, 10 Sep 2017 18:31:24 +0200","from localhost (unknown [132.68.137.153])\n\tby correu-1.ac.upc.es (Postfix) with ESMTPSA id B940F1B8;\n\tSun, 10 Sep 2017 18:31:18 +0200 (CEST)"],"From":"=?utf-8?b?TGx1w61z?= Vilanova <vilanova@ac.upc.edu>","To":"qemu-devel@nongnu.org","Date":"Sun, 10 Sep 2017 19:31:17 +0300","Message-Id":"<150506107741.19604.8328467942268087647.stgit@frigg.lan>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<150505986682.19604.11937392314067517230.stgit@frigg.lan>","References":"<150505986682.19604.11937392314067517230.stgit@frigg.lan>","User-Agent":"StGit/0.18","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","X-MIME-Autoconverted":"from 8bit to quoted-printable by roura.ac.upc.es id\n\tv8AGVOxX020554","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy]","X-Received-From":"147.83.33.10","Subject":"[Qemu-devel] [PATCH 5/7] trace: Add event \"guest_bbl_after\"","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"<qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<http://lists.nongnu.org/archive/html/qemu-devel/>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Cc":"Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <rth@twiddle.net>,\n\tStefan Hajnoczi <stefanha@redhat.com>,\n\tPeter Crosthwaite <crosthwaite.peter@gmail.com>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"},"content":"Need to use \"TCG inlining\" to avoid showing a trace entry for each exit\npoint (up to two per BBL).\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\n---\n accel/tcg/translator.c    |   54 +++++++++++++++++++++++++++++++++++++++++++++\n include/exec/translator.h |   22 ++++++++++++++++++\n tcg/tcg-op.c              |    2 ++\n tcg/tcg-op.h              |    1 +\n tcg/tcg.h                 |    5 ++++\n trace-events              |   11 +++++++++\n 6 files changed, 94 insertions(+), 1 deletion(-)","diff":"diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c\nindex 6598931171..d66d601c89 100644\n--- a/accel/tcg/translator.c\n+++ b/accel/tcg/translator.c\n@@ -35,6 +35,7 @@ void translator_loop_temp_check(DisasContextBase *db)\n void translator_loop(const TranslatorOps *ops, DisasContextBase *db,\n                      CPUState *cpu, TranslationBlock *tb)\n {\n+    target_ulong pc_bbl;\n     int max_insns;\n \n     /* Initialize DisasContext */\n@@ -63,6 +64,11 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,\n     /* Reset the temp count so that we can identify leaks */\n     tcg_clear_temp_count();\n \n+    /* Tracking gen_goto_tb / gen_exit_tb */\n+    pc_bbl = db->pc_first;\n+    tcg_ctx.disas.seen_goto_tb = false;\n+    tcg_ctx.disas.in_guest_code = false;\n+\n     /* Start translating.  */\n     gen_tb_start(db->tb);\n     ops->tb_start(db, cpu);\n@@ -74,6 +80,11 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,\n         int insn_size_opcode_idx;\n \n         db->num_insns++;\n+        if (db->num_insns == 1) {\n+            tcg_ctx.disas.in_guest_code = true;\n+            tcg_ctx.disas.inline_label = NULL;\n+        }\n+\n         ops->insn_start(db, cpu);\n         tcg_debug_assert(db->is_jmp == DISAS_NEXT);  /* no early exit */\n \n@@ -144,6 +155,22 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,\n         }\n     }\n \n+    /* Tracing after */\n+    if (TRACE_GUEST_BBL_AFTER_ENABLED) {\n+        tcg_ctx.disas.in_guest_code = false;\n+        if (tcg_ctx.disas.inline_label == NULL) {\n+            tcg_ctx.disas.inline_label = gen_new_inline_label();\n+        }\n+\n+        gen_set_inline_region_begin(tcg_ctx.disas.inline_label);\n+\n+        if (TRACE_GUEST_BBL_AFTER_ENABLED) {\n+            trace_guest_bbl_after_tcg(cpu, tcg_ctx.tcg_env, pc_bbl);\n+        }\n+\n+        gen_set_inline_region_end(tcg_ctx.disas.inline_label);\n+    }\n+\n     /* Emit code to exit the TB, as indicated by db->is_jmp.  */\n     ops->tb_stop(db, cpu);\n     gen_tb_end(db->tb, db->num_insns);\n@@ -163,3 +190,30 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,\n     }\n #endif\n }\n+\n+\n+void translator__gen_goto_tb(TCGContext *ctx)\n+{\n+    if (ctx->disas.in_guest_code &&\n+        (TRACE_GUEST_BBL_AFTER_ENABLED)) {\n+        if (ctx->disas.inline_label == NULL) {\n+            ctx->disas.inline_label = gen_new_inline_label();\n+        }\n+        gen_set_inline_point(ctx->disas.inline_label);\n+        /* disable next exit_tb */\n+        ctx->disas.seen_goto_tb = true;\n+    }\n+}\n+\n+void translator__gen_exit_tb(TCGContext *ctx)\n+{\n+    if (ctx->disas.in_guest_code && !ctx->disas.seen_goto_tb &&\n+        (TRACE_GUEST_BBL_AFTER_ENABLED)) {\n+        if (ctx->disas.inline_label == NULL) {\n+            ctx->disas.inline_label = gen_new_inline_label();\n+        }\n+        gen_set_inline_point(ctx->disas.inline_label);\n+        /* enable next exit_tb */\n+        ctx->disas.seen_goto_tb = false;\n+    }\n+}\ndiff --git a/include/exec/translator.h b/include/exec/translator.h\nindex e2dc2a04ae..83aeea59a1 100644\n--- a/include/exec/translator.h\n+++ b/include/exec/translator.h\n@@ -20,7 +20,6 @@\n \n \n #include \"exec/exec-all.h\"\n-#include \"tcg/tcg.h\"\n \n \n /**\n@@ -71,6 +70,21 @@ typedef struct DisasContextBase {\n     bool singlestep_enabled;\n } DisasContextBase;\n \n+/**\n+ * TCGContextDisas:\n+ * @seen_goto_tb: Whether we've seen a call to tcg_gen_goto_tb().\n+ * @in_guest_code: Whether we're generating guest code (or supporting\n+ *                 boilerplate otherwise).\n+ * @inline_label: Inline label.\n+ *\n+ * Extensions to #TCGContext specific to the generic translation framework.\n+ */\n+typedef struct TCGContextDisas {\n+    bool seen_goto_tb;\n+    bool in_guest_code;\n+    TCGInlineLabel *inline_label;\n+} TCGContextDisas;\n+\n /**\n  * TranslatorOps:\n  * @init_disas_context:\n@@ -117,6 +131,8 @@ typedef struct TranslatorOps {\n     void (*disas_log)(const DisasContextBase *db, CPUState *cpu);\n } TranslatorOps;\n \n+#include \"tcg/tcg.h\"\n+\n /**\n  * translator_loop:\n  * @ops: Target-specific operations.\n@@ -141,4 +157,8 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,\n \n void translator_loop_temp_check(DisasContextBase *db);\n \n+/* Internal functions to hook tracing into */\n+void translator__gen_goto_tb(TCGContext *ctx);\n+void translator__gen_exit_tb(TCGContext *ctx);\n+\n #endif  /* EXEC__TRANSLATOR_H */\ndiff --git a/tcg/tcg-op.c b/tcg/tcg-op.c\nindex 688d91755b..575b4faf84 100644\n--- a/tcg/tcg-op.c\n+++ b/tcg/tcg-op.c\n@@ -2578,6 +2578,8 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg)\n \n void tcg_gen_goto_tb(unsigned idx)\n {\n+    translator__gen_goto_tb(&tcg_ctx);\n+\n     /* We only support two chained exits.  */\n     tcg_debug_assert(idx <= 1);\n #ifdef CONFIG_DEBUG_TCG\ndiff --git a/tcg/tcg-op.h b/tcg/tcg-op.h\nindex da3784f8f2..9ab1497bc1 100644\n--- a/tcg/tcg-op.h\n+++ b/tcg/tcg-op.h\n@@ -817,6 +817,7 @@ static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,\n \n static inline void tcg_gen_exit_tb(uintptr_t val)\n {\n+    translator__gen_exit_tb(&tcg_ctx);\n     tcg_gen_op1i(INDEX_op_exit_tb, val);\n }\n \ndiff --git a/tcg/tcg.h b/tcg/tcg.h\nindex c6e3c6e68d..6483ed75d6 100644\n--- a/tcg/tcg.h\n+++ b/tcg/tcg.h\n@@ -655,6 +655,8 @@ QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14));\n /* Make sure that we don't overflow 64 bits without noticing.  */\n QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8);\n \n+#include \"exec/translator.h\"\n+\n struct TCGContext {\n     uint8_t *pool_cur, *pool_end;\n     TCGPool *pool_first, *pool_current, *pool_first_large;\n@@ -730,6 +732,9 @@ struct TCGContext {\n     CPUState *cpu;                      /* *_trans */\n     TCGv_env tcg_env;                   /* *_exec  */\n \n+    /* Used by generic gen_intermediate_code */\n+    TCGContextDisas disas;\n+\n     /* These structures are private to tcg-target.inc.c.  */\n #ifdef TCG_TARGET_NEED_LDST_LABELS\n     struct TCGLabelQemuLdst *ldst_labels;\ndiff --git a/trace-events b/trace-events\nindex 4e61697297..ce54bb4993 100644\n--- a/trace-events\n+++ b/trace-events\n@@ -99,6 +99,17 @@ vcpu guest_cpu_reset(void)\n # Targets: TCG(all)\n vcpu tcg guest_bbl_before(uint64_t vaddr) \"vaddr=0x%016\"PRIx64, \"vaddr=0x%016\"PRIx64\n \n+# @vaddr: BBL's starting virtual address\n+#\n+# Mark end of BBL execution (after the BBL-exiting instruction).\n+#\n+# NOTE: This event might not be raised if the BBL ends unexpectedly (e.g.,\n+#       triggers an exception).\n+#\n+# Mode: user, softmmu\n+# Targets: TCG(all)\n+vcpu tcg guest_bbl_after(uint64_t vaddr) \"vaddr=0x%016\"PRIx64, \"vaddr=0x%016\"PRIx64\n+\n # @vaddr: Instruction's virtual address\n #\n # Mark start of instruction execution (before anything gets really executed).\n","prefixes":["5/7"]}