{"id":811527,"url":"http://patchwork.ozlabs.org/api/patches/811527/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-19-david@gibson.dropbear.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908103558.31632-19-david@gibson.dropbear.id.au>","list_archive_url":null,"date":"2017-09-08T10:35:36","name":"[PULL,18/40] booke206: fix tlbnps for fixed size TLB","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c2cde7abf010537a8a7c3e271c5017ba7aca5ac9","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/?format=json","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-19-david@gibson.dropbear.id.au/mbox/","series":[{"id":2179,"url":"http://patchwork.ozlabs.org/api/series/2179/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2179","date":"2017-09-08T10:35:20","name":"[PULL,01/40] hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->dev","version":1,"mbox":"http://patchwork.ozlabs.org/series/2179/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811527/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811527/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"FaBqhYcA\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpZ9r26GJz9s81\n\tfor ;\n\tFri, 8 Sep 2017 21:00:48 +1000 (AEST)","from localhost ([::1]:44564 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dqH1h-0006gw-Hl\n\tfor incoming@patchwork.ozlabs.org; Fri, 08 Sep 2017 07:00:45 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:58668)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dqGe5-00028i-AG\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:29 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dqGe0-0003EJ-F5\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:21 -0400","from ozlabs.org ([2401:3900:2:1::2]:54369)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dqGe0-0003Bn-02; Fri, 08 Sep 2017 06:36:16 -0400","by ozlabs.org (Postfix, from userid 1007)\n\tid 3xpYdL5f8wz9t4c; Fri, 8 Sep 2017 20:36:04 +1000 (AEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1504866966;\n\tbh=08F7meoLgnirL0dn0DGt7ZuONGT7wTakwVjKuIjq5Wg=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=FaBqhYcAh0tyJz2J8lT/Al3TXMtlN0ikeCVvvs8LhrIeY9UcdlsemuU+DYD/dGGFv\n\tOjCLIjYXdpwdcKD5WWGITX8nU9F5d7wKzkKJ6ggRbyIXKRjjSRENjtRbtgBKGKINAF\n\t6VvaZBAwkvoLM9lkPzxb0I1cQfPISOKJmxD4aQWY=","From":"David Gibson ","To":"peter.maydell@linaro.org","Date":"Fri, 8 Sep 2017 20:35:36 +1000","Message-Id":"<20170908103558.31632-19-david@gibson.dropbear.id.au>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170908103558.31632-1-david@gibson.dropbear.id.au>","References":"<20170908103558.31632-1-david@gibson.dropbear.id.au>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2401:3900:2:1::2","Subject":"[Qemu-devel] [PULL 18/40] booke206: fix tlbnps for fixed size TLB","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de,\n\tmdroth@linux.vnet.ibm.com,\n\tKONRAD Frederic , \n\tqemu-ppc@nongnu.org, imammedo@redhat.com, sam.bobroff@au1.ibm.com,\n\tDavid Gibson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: KONRAD Frederic \n\nSome OS don't populate the TSIZE field when using a fixed size TLB which result\nin a 1KB TLB. When the TLB is a fixed size TLB the TSIZE field should be\nignored.\n\nFix this wrong behavior with MAV 2.0.\n\nSigned-off-by: KONRAD Frederic \nSigned-off-by: David Gibson \n---\n target/ppc/cpu.h | 22 ++++++++++++++++++++++\n target/ppc/mmu_helper.c | 16 ++++++++++------\n 2 files changed, 32 insertions(+), 6 deletions(-)","diff":"diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h\nindex 21f0ddd056..042372c5ad 100644\n--- a/target/ppc/cpu.h\n+++ b/target/ppc/cpu.h\n@@ -2491,6 +2491,28 @@ static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)\n return ret;\n }\n \n+static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,\n+ ppcmas_tlb_t *tlb)\n+{\n+ uint8_t i;\n+ int32_t tsize = -1;\n+\n+ for (i = 0; i < 32; i++) {\n+ if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {\n+ if (tsize == -1) {\n+ tsize = i;\n+ } else {\n+ return;\n+ }\n+ }\n+ }\n+\n+ /* TLBnPS unimplemented? Odd.. */\n+ assert(tsize != -1);\n+ tlb->mas1 &= ~MAS1_TSIZE_MASK;\n+ tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;\n+}\n+\n #endif\n \n static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)\ndiff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c\nindex f06b9382b4..2a1f9902c9 100644\n--- a/target/ppc/mmu_helper.c\n+++ b/target/ppc/mmu_helper.c\n@@ -2632,12 +2632,16 @@ void helper_booke206_tlbwe(CPUPPCState *env)\n env->spr[SPR_BOOKE_MAS3];\n tlb->mas1 = env->spr[SPR_BOOKE_MAS1];\n \n- /* MAV 1.0 only */\n- if (!(tlbncfg & TLBnCFG_AVAIL)) {\n- /* force !AVAIL TLB entries to correct page size */\n- tlb->mas1 &= ~MAS1_TSIZE_MASK;\n- /* XXX can be configured in MMUCSR0 */\n- tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;\n+ if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {\n+ /* For TLB which has a fixed size TSIZE is ignored with MAV2 */\n+ booke206_fixed_size_tlbn(env, tlbn, tlb);\n+ } else {\n+ if (!(tlbncfg & TLBnCFG_AVAIL)) {\n+ /* force !AVAIL TLB entries to correct page size */\n+ tlb->mas1 &= ~MAS1_TSIZE_MASK;\n+ /* XXX can be configured in MMUCSR0 */\n+ tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;\n+ }\n }\n \n /* Make a mask from TLB size to discard invalid bits in EPN field */\n","prefixes":["PULL","18/40"]}