{"id":811520,"url":"http://patchwork.ozlabs.org/api/patches/811520/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-26-david@gibson.dropbear.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908103558.31632-26-david@gibson.dropbear.id.au>","list_archive_url":null,"date":"2017-09-08T10:35:43","name":"[PULL,25/40] ppc4xx_i2c: QOMify","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"54b09eed8f141f5c90b1e9f52217a38a73764645","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/?format=json","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-26-david@gibson.dropbear.id.au/mbox/","series":[{"id":2179,"url":"http://patchwork.ozlabs.org/api/series/2179/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2179","date":"2017-09-08T10:35:20","name":"[PULL,01/40] hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->dev","version":1,"mbox":"http://patchwork.ozlabs.org/series/2179/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811520/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811520/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"NxPTSPwS\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpZ2R6M0cz9s3w\n\tfor ;\n\tFri, 8 Sep 2017 20:54:23 +1000 (AEST)","from localhost ([::1]:44531 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dqGvV-0001mI-Vo\n\tfor incoming@patchwork.ozlabs.org; Fri, 08 Sep 2017 06:54:22 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:58789)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dqGeA-0002Db-8Z\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:37 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dqGe3-0003I5-66\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:26 -0400","from ozlabs.org ([2401:3900:2:1::2]:40653)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dqGe2-0003FE-Js; Fri, 08 Sep 2017 06:36:19 -0400","by ozlabs.org (Postfix, from userid 1007)\n\tid 3xpYdN5fHBz9t5b; Fri, 8 Sep 2017 20:36:05 +1000 (AEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1504866968;\n\tbh=sDYoXSJcNq84CgU6td9AwRufjDifSc+lTqg8SyPY8vU=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=NxPTSPwSktxxWyAhe1gh7XD90/EhclnjukceHwehxh5RfjKNGx7a1keoQl2gvbGjZ\n\tMjpM0W2ZYXDt1miPvCVjtP6Z9VqBiPMMCWulrv6k9qrE7selSDdtNqf4TOgLZVByS8\n\t/gbJAOIOlNnMN6vH+XAh6f5x8Y5w6sCLX1ot2g2Q=","From":"David Gibson ","To":"peter.maydell@linaro.org","Date":"Fri, 8 Sep 2017 20:35:43 +1000","Message-Id":"<20170908103558.31632-26-david@gibson.dropbear.id.au>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170908103558.31632-1-david@gibson.dropbear.id.au>","References":"<20170908103558.31632-1-david@gibson.dropbear.id.au>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2401:3900:2:1::2","Subject":"[Qemu-devel] [PULL 25/40] ppc4xx_i2c: QOMify","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de,\n\tmdroth@linux.vnet.ibm.com, qemu-ppc@nongnu.org,\n\timammedo@redhat.com, sam.bobroff@au1.ibm.com,\n\tDavid Gibson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: BALATON Zoltan \n\nSigned-off-by: BALATON Zoltan \nSigned-off-by: David Gibson \n---\n hw/ppc/ppc405.h | 2 -\n hw/ppc/ppc405_uc.c | 5 +-\n hw/ppc/ppc4xx_i2c.c | 154 ++++++++++++++------------------------------\n include/hw/i2c/ppc4xx_i2c.h | 61 ++++++++++++++++++\n 4 files changed, 113 insertions(+), 109 deletions(-)\n create mode 100644 include/hw/i2c/ppc4xx_i2c.h","diff":"diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h\nindex 61ec739ebf..a9ffc87f19 100644\n--- a/hw/ppc/ppc405.h\n+++ b/hw/ppc/ppc405.h\n@@ -59,8 +59,6 @@ struct ppc4xx_bd_info_t {\n ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,\n uint32_t flags);\n \n-void ppc405_i2c_init(hwaddr base, qemu_irq irq);\n-\n CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,\n MemoryRegion ram_memories[4],\n hwaddr ram_bases[4],\ndiff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c\nindex 3925e4c60b..8f44cb46d0 100644\n--- a/hw/ppc/ppc405_uc.c\n+++ b/hw/ppc/ppc405_uc.c\n@@ -28,6 +28,7 @@\n #include \"hw/hw.h\"\n #include \"hw/ppc/ppc.h\"\n #include \"hw/boards.h\"\n+#include \"hw/i2c/ppc4xx_i2c.h\"\n #include \"ppc405.h\"\n #include \"hw/char/serial.h\"\n #include \"qemu/timer.h\"\n@@ -1663,7 +1664,7 @@ CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,\n DEVICE_BIG_ENDIAN);\n }\n /* IIC controller */\n- ppc405_i2c_init(0xef600500, pic[2]);\n+ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);\n /* GPIO */\n ppc405_gpio_init(0xef600700);\n /* CPU control */\n@@ -2010,7 +2011,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,\n dma_irqs[3] = pic[8];\n ppc405_dma_init(env, dma_irqs);\n /* IIC controller */\n- ppc405_i2c_init(0xef600500, pic[2]);\n+ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);\n /* GPIO */\n ppc405_gpio_init(0xef600700);\n /* Serial ports */\ndiff --git a/hw/ppc/ppc4xx_i2c.c b/hw/ppc/ppc4xx_i2c.c\nindex 15f2dea69e..5a6bde951e 100644\n--- a/hw/ppc/ppc4xx_i2c.c\n+++ b/hw/ppc/ppc4xx_i2c.c\n@@ -27,42 +27,20 @@\n #include \"qemu-common.h\"\n #include \"cpu.h\"\n #include \"hw/hw.h\"\n-#include \"exec/address-spaces.h\"\n-#include \"hw/ppc/ppc.h\"\n-#include \"ppc405.h\"\n+#include \"hw/i2c/ppc4xx_i2c.h\"\n \n /*#define DEBUG_I2C*/\n \n-typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;\n-struct ppc4xx_i2c_t {\n- qemu_irq irq;\n- MemoryRegion iomem;\n- uint8_t mdata;\n- uint8_t lmadr;\n- uint8_t hmadr;\n- uint8_t cntl;\n- uint8_t mdcntl;\n- uint8_t sts;\n- uint8_t extsts;\n- uint8_t sdata;\n- uint8_t lsadr;\n- uint8_t hsadr;\n- uint8_t clkdiv;\n- uint8_t intrmsk;\n- uint8_t xfrcnt;\n- uint8_t xtcntlss;\n- uint8_t directcntl;\n-};\n+#define PPC4xx_I2C_MEM_SIZE 0x11\n \n-static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr addr)\n+static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)\n {\n- ppc4xx_i2c_t *i2c;\n- uint32_t ret;\n+ PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);\n+ uint64_t ret;\n \n #ifdef DEBUG_I2C\n printf(\"%s: addr \" TARGET_FMT_plx \"\\n\", __func__, addr);\n #endif\n- i2c = opaque;\n switch (addr) {\n case 0x00:\n /*i2c_readbyte(&i2c->mdata);*/\n@@ -115,22 +93,20 @@ static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr addr)\n break;\n }\n #ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \" %02\" PRIx32 \"\\n\", __func__, addr, ret);\n+ printf(\"%s: addr \" TARGET_FMT_plx \" %02\" PRIx64 \"\\n\", __func__, addr, ret);\n #endif\n \n return ret;\n }\n \n-static void ppc4xx_i2c_writeb(void *opaque,\n- hwaddr addr, uint32_t value)\n+static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,\n+ unsigned int size)\n {\n- ppc4xx_i2c_t *i2c;\n-\n+ PPC4xxI2CState *i2c = opaque;\n #ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx32 \"\\n\", __func__, addr,\n- value);\n+ printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx64 \"\\n\",\n+ __func__, addr, value);\n #endif\n- i2c = opaque;\n switch (addr) {\n case 0x00:\n i2c->mdata = value;\n@@ -181,71 +157,20 @@ static void ppc4xx_i2c_writeb(void *opaque,\n }\n }\n \n-static uint32_t ppc4xx_i2c_readw(void *opaque, hwaddr addr)\n-{\n- uint32_t ret;\n-\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \"\\n\", __func__, addr);\n-#endif\n- ret = ppc4xx_i2c_readb(opaque, addr) << 8;\n- ret |= ppc4xx_i2c_readb(opaque, addr + 1);\n-\n- return ret;\n-}\n-\n-static void ppc4xx_i2c_writew(void *opaque,\n- hwaddr addr, uint32_t value)\n-{\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx32 \"\\n\", __func__, addr,\n- value);\n-#endif\n- ppc4xx_i2c_writeb(opaque, addr, value >> 8);\n- ppc4xx_i2c_writeb(opaque, addr + 1, value);\n-}\n-\n-static uint32_t ppc4xx_i2c_readl(void *opaque, hwaddr addr)\n-{\n- uint32_t ret;\n-\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \"\\n\", __func__, addr);\n-#endif\n- ret = ppc4xx_i2c_readb(opaque, addr) << 24;\n- ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;\n- ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;\n- ret |= ppc4xx_i2c_readb(opaque, addr + 3);\n-\n- return ret;\n-}\n-\n-static void ppc4xx_i2c_writel(void *opaque,\n- hwaddr addr, uint32_t value)\n-{\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx32 \"\\n\", __func__, addr,\n- value);\n-#endif\n- ppc4xx_i2c_writeb(opaque, addr, value >> 24);\n- ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);\n- ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);\n- ppc4xx_i2c_writeb(opaque, addr + 3, value);\n-}\n-\n-static const MemoryRegionOps i2c_ops = {\n- .old_mmio = {\n- .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },\n- .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },\n- },\n+static const MemoryRegionOps ppc4xx_i2c_ops = {\n+ .read = ppc4xx_i2c_readb,\n+ .write = ppc4xx_i2c_writeb,\n+ .valid.min_access_size = 1,\n+ .valid.max_access_size = 4,\n+ .impl.min_access_size = 1,\n+ .impl.max_access_size = 1,\n .endianness = DEVICE_NATIVE_ENDIAN,\n };\n \n-static void ppc4xx_i2c_reset(void *opaque)\n+static void ppc4xx_i2c_reset(DeviceState *s)\n {\n- ppc4xx_i2c_t *i2c;\n+ PPC4xxI2CState *i2c = PPC4xx_I2C(s);\n \n- i2c = opaque;\n i2c->mdata = 0x00;\n i2c->sdata = 0x00;\n i2c->cntl = 0x00;\n@@ -257,16 +182,35 @@ static void ppc4xx_i2c_reset(void *opaque)\n i2c->directcntl = 0x0F;\n }\n \n-void ppc405_i2c_init(hwaddr base, qemu_irq irq)\n+static void ppc4xx_i2c_init(Object *o)\n {\n- ppc4xx_i2c_t *i2c;\n+ PPC4xxI2CState *s = PPC4xx_I2C(o);\n \n- i2c = g_malloc0(sizeof(ppc4xx_i2c_t));\n- i2c->irq = irq;\n-#ifdef DEBUG_I2C\n- printf(\"%s: offset \" TARGET_FMT_plx \"\\n\", __func__, base);\n-#endif\n- memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, \"i2c\", 0x011);\n- memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);\n- qemu_register_reset(ppc4xx_i2c_reset, i2c);\n+ memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,\n+ TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);\n+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);\n+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);\n+ s->bus = i2c_init_bus(DEVICE(s), \"i2c\");\n }\n+\n+static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->reset = ppc4xx_i2c_reset;\n+}\n+\n+static const TypeInfo ppc4xx_i2c_type_info = {\n+ .name = TYPE_PPC4xx_I2C,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(PPC4xxI2CState),\n+ .instance_init = ppc4xx_i2c_init,\n+ .class_init = ppc4xx_i2c_class_init,\n+};\n+\n+static void ppc4xx_i2c_register_types(void)\n+{\n+ type_register_static(&ppc4xx_i2c_type_info);\n+}\n+\n+type_init(ppc4xx_i2c_register_types)\ndiff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h\nnew file mode 100644\nindex 0000000000..e53042f6d4\n--- /dev/null\n+++ b/include/hw/i2c/ppc4xx_i2c.h\n@@ -0,0 +1,61 @@\n+/*\n+ * PPC4xx I2C controller emulation\n+ *\n+ * Copyright (c) 2007 Jocelyn Mayer\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#ifndef PPC4XX_I2C_H\n+#define PPC4XX_I2C_H\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu-common.h\"\n+#include \"hw/sysbus.h\"\n+#include \"hw/i2c/i2c.h\"\n+\n+#define TYPE_PPC4xx_I2C \"ppc4xx-i2c\"\n+#define PPC4xx_I2C(obj) OBJECT_CHECK(PPC4xxI2CState, (obj), TYPE_PPC4xx_I2C)\n+\n+typedef struct PPC4xxI2CState {\n+ /*< private >*/\n+ SysBusDevice parent_obj;\n+\n+ /*< public >*/\n+ I2CBus *bus;\n+ qemu_irq irq;\n+ MemoryRegion iomem;\n+ uint8_t mdata;\n+ uint8_t lmadr;\n+ uint8_t hmadr;\n+ uint8_t cntl;\n+ uint8_t mdcntl;\n+ uint8_t sts;\n+ uint8_t extsts;\n+ uint8_t sdata;\n+ uint8_t lsadr;\n+ uint8_t hsadr;\n+ uint8_t clkdiv;\n+ uint8_t intrmsk;\n+ uint8_t xfrcnt;\n+ uint8_t xtcntlss;\n+ uint8_t directcntl;\n+} PPC4xxI2CState;\n+\n+#endif /* PPC4XX_I2C_H */\n","prefixes":["PULL","25/40"]}