{"id":811517,"url":"http://patchwork.ozlabs.org/api/patches/811517/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-25-david@gibson.dropbear.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908103558.31632-25-david@gibson.dropbear.id.au>","list_archive_url":null,"date":"2017-09-08T10:35:42","name":"[PULL,24/40] ppc4xx: Split off 4xx I2C emulation from ppc405_uc to its own file","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7f07614a76581696cb95b46a5b10ec883f2e55ae","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/?format=json","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-25-david@gibson.dropbear.id.au/mbox/","series":[{"id":2179,"url":"http://patchwork.ozlabs.org/api/series/2179/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2179","date":"2017-09-08T10:35:20","name":"[PULL,01/40] hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->dev","version":1,"mbox":"http://patchwork.ozlabs.org/series/2179/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811517/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811517/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"XB1br7jG\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpZ0p074Qz9s3w\n\tfor ;\n\tFri, 8 Sep 2017 20:52:58 +1000 (AEST)","from localhost ([::1]:44524 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dqGu8-0000Hh-3C\n\tfor incoming@patchwork.ozlabs.org; Fri, 08 Sep 2017 06:52:56 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:58823)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dqGeB-0002Ew-CL\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:38 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dqGe3-0003Ih-MY\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:27 -0400","from ozlabs.org ([2401:3900:2:1::2]:52313)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dqGe3-0003Fc-3x; Fri, 08 Sep 2017 06:36:19 -0400","by ozlabs.org (Postfix, from userid 1007)\n\tid 3xpYdP2QJ4z9t4t; Fri, 8 Sep 2017 20:36:05 +1000 (AEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1504866969;\n\tbh=XRHvHtYi1lw2vd6Iy4LgI0gc3GnSZVfCyi5Vhbr4jDI=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=XB1br7jGqTDWkdLhusmzl7mUhkLHmEqqR0pNsGU1wF7uaf/7Tw+xBGH+AwM32qACY\n\tXqTEEQ6srnZRS4aH/l4EduWAOguTUDCqVqxGQKMIpYKtaMjpGoEWx3hPr6+wNy9mE3\n\tSfNs85NPYBPZtHXTrFz/TYSO9XvyApTsCj7wq9Qk=","From":"David Gibson ","To":"peter.maydell@linaro.org","Date":"Fri, 8 Sep 2017 20:35:42 +1000","Message-Id":"<20170908103558.31632-25-david@gibson.dropbear.id.au>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170908103558.31632-1-david@gibson.dropbear.id.au>","References":"<20170908103558.31632-1-david@gibson.dropbear.id.au>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2401:3900:2:1::2","Subject":"[Qemu-devel] [PULL 24/40] ppc4xx: Split off 4xx I2C emulation from\n\tppc405_uc to its own file","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de,\n\tmdroth@linux.vnet.ibm.com, qemu-ppc@nongnu.org,\n\timammedo@redhat.com, sam.bobroff@au1.ibm.com,\n\tDavid Gibson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: BALATON Zoltan \n\nThis device appears in other SoCs as well not just in 405 ones and\nsubsequent patches will modify it, so move it out of ppc405_uc.c in\npreparation\n\nSigned-off-by: BALATON Zoltan \nSigned-off-by: David Gibson \n---\n hw/ppc/Makefile.objs | 2 +-\n hw/ppc/ppc405.h | 2 +\n hw/ppc/ppc405_uc.c | 241 ---------------------------------------------\n hw/ppc/ppc4xx_i2c.c | 272 +++++++++++++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 275 insertions(+), 242 deletions(-)\n create mode 100644 hw/ppc/ppc4xx_i2c.c","diff":"diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs\nindex 7efc686748..207721647a 100644\n--- a/hw/ppc/Makefile.objs\n+++ b/hw/ppc/Makefile.objs\n@@ -13,7 +13,7 @@ endif\n obj-$(CONFIG_PSERIES) += spapr_rtas_ddw.o\n # PowerPC 4xx boards\n obj-y += ppc405_boards.o ppc4xx_devs.o ppc405_uc.o ppc440_bamboo.o\n-obj-y += ppc4xx_pci.o\n+obj-y += ppc4xx_pci.o ppc4xx_i2c.o\n # PReP\n obj-$(CONFIG_PREP) += prep.o\n obj-$(CONFIG_PREP) += prep_systemio.o\ndiff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h\nindex a9ffc87f19..61ec739ebf 100644\n--- a/hw/ppc/ppc405.h\n+++ b/hw/ppc/ppc405.h\n@@ -59,6 +59,8 @@ struct ppc4xx_bd_info_t {\n ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,\n uint32_t flags);\n \n+void ppc405_i2c_init(hwaddr base, qemu_irq irq);\n+\n CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,\n MemoryRegion ram_memories[4],\n hwaddr ram_bases[4],\ndiff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c\nindex 03856d573f..3925e4c60b 100644\n--- a/hw/ppc/ppc405_uc.c\n+++ b/hw/ppc/ppc405_uc.c\n@@ -40,7 +40,6 @@\n //#define DEBUG_GPIO\n //#define DEBUG_SERIAL\n //#define DEBUG_OCM\n-//#define DEBUG_I2C\n //#define DEBUG_GPT\n //#define DEBUG_CLOCKS\n //#define DEBUG_CLOCKS_LL\n@@ -993,246 +992,6 @@ static void ppc405_ocm_init(CPUPPCState *env)\n }\n \n /*****************************************************************************/\n-/* I2C controller */\n-typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;\n-struct ppc4xx_i2c_t {\n- qemu_irq irq;\n- MemoryRegion iomem;\n- uint8_t mdata;\n- uint8_t lmadr;\n- uint8_t hmadr;\n- uint8_t cntl;\n- uint8_t mdcntl;\n- uint8_t sts;\n- uint8_t extsts;\n- uint8_t sdata;\n- uint8_t lsadr;\n- uint8_t hsadr;\n- uint8_t clkdiv;\n- uint8_t intrmsk;\n- uint8_t xfrcnt;\n- uint8_t xtcntlss;\n- uint8_t directcntl;\n-};\n-\n-static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)\n-{\n- ppc4xx_i2c_t *i2c;\n- uint32_t ret;\n-\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \"\\n\", __func__, addr);\n-#endif\n- i2c = opaque;\n- switch (addr) {\n- case 0x00:\n- // i2c_readbyte(&i2c->mdata);\n- ret = i2c->mdata;\n- break;\n- case 0x02:\n- ret = i2c->sdata;\n- break;\n- case 0x04:\n- ret = i2c->lmadr;\n- break;\n- case 0x05:\n- ret = i2c->hmadr;\n- break;\n- case 0x06:\n- ret = i2c->cntl;\n- break;\n- case 0x07:\n- ret = i2c->mdcntl;\n- break;\n- case 0x08:\n- ret = i2c->sts;\n- break;\n- case 0x09:\n- ret = i2c->extsts;\n- break;\n- case 0x0A:\n- ret = i2c->lsadr;\n- break;\n- case 0x0B:\n- ret = i2c->hsadr;\n- break;\n- case 0x0C:\n- ret = i2c->clkdiv;\n- break;\n- case 0x0D:\n- ret = i2c->intrmsk;\n- break;\n- case 0x0E:\n- ret = i2c->xfrcnt;\n- break;\n- case 0x0F:\n- ret = i2c->xtcntlss;\n- break;\n- case 0x10:\n- ret = i2c->directcntl;\n- break;\n- default:\n- ret = 0x00;\n- break;\n- }\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \" %02\" PRIx32 \"\\n\", __func__, addr, ret);\n-#endif\n-\n- return ret;\n-}\n-\n-static void ppc4xx_i2c_writeb (void *opaque,\n- hwaddr addr, uint32_t value)\n-{\n- ppc4xx_i2c_t *i2c;\n-\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx32 \"\\n\", __func__, addr,\n- value);\n-#endif\n- i2c = opaque;\n- switch (addr) {\n- case 0x00:\n- i2c->mdata = value;\n- // i2c_sendbyte(&i2c->mdata);\n- break;\n- case 0x02:\n- i2c->sdata = value;\n- break;\n- case 0x04:\n- i2c->lmadr = value;\n- break;\n- case 0x05:\n- i2c->hmadr = value;\n- break;\n- case 0x06:\n- i2c->cntl = value;\n- break;\n- case 0x07:\n- i2c->mdcntl = value & 0xDF;\n- break;\n- case 0x08:\n- i2c->sts &= ~(value & 0x0A);\n- break;\n- case 0x09:\n- i2c->extsts &= ~(value & 0x8F);\n- break;\n- case 0x0A:\n- i2c->lsadr = value;\n- break;\n- case 0x0B:\n- i2c->hsadr = value;\n- break;\n- case 0x0C:\n- i2c->clkdiv = value;\n- break;\n- case 0x0D:\n- i2c->intrmsk = value;\n- break;\n- case 0x0E:\n- i2c->xfrcnt = value & 0x77;\n- break;\n- case 0x0F:\n- i2c->xtcntlss = value;\n- break;\n- case 0x10:\n- i2c->directcntl = value & 0x7;\n- break;\n- }\n-}\n-\n-static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)\n-{\n- uint32_t ret;\n-\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \"\\n\", __func__, addr);\n-#endif\n- ret = ppc4xx_i2c_readb(opaque, addr) << 8;\n- ret |= ppc4xx_i2c_readb(opaque, addr + 1);\n-\n- return ret;\n-}\n-\n-static void ppc4xx_i2c_writew (void *opaque,\n- hwaddr addr, uint32_t value)\n-{\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx32 \"\\n\", __func__, addr,\n- value);\n-#endif\n- ppc4xx_i2c_writeb(opaque, addr, value >> 8);\n- ppc4xx_i2c_writeb(opaque, addr + 1, value);\n-}\n-\n-static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)\n-{\n- uint32_t ret;\n-\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \"\\n\", __func__, addr);\n-#endif\n- ret = ppc4xx_i2c_readb(opaque, addr) << 24;\n- ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;\n- ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;\n- ret |= ppc4xx_i2c_readb(opaque, addr + 3);\n-\n- return ret;\n-}\n-\n-static void ppc4xx_i2c_writel (void *opaque,\n- hwaddr addr, uint32_t value)\n-{\n-#ifdef DEBUG_I2C\n- printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx32 \"\\n\", __func__, addr,\n- value);\n-#endif\n- ppc4xx_i2c_writeb(opaque, addr, value >> 24);\n- ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);\n- ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);\n- ppc4xx_i2c_writeb(opaque, addr + 3, value);\n-}\n-\n-static const MemoryRegionOps i2c_ops = {\n- .old_mmio = {\n- .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },\n- .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },\n- },\n- .endianness = DEVICE_NATIVE_ENDIAN,\n-};\n-\n-static void ppc4xx_i2c_reset (void *opaque)\n-{\n- ppc4xx_i2c_t *i2c;\n-\n- i2c = opaque;\n- i2c->mdata = 0x00;\n- i2c->sdata = 0x00;\n- i2c->cntl = 0x00;\n- i2c->mdcntl = 0x00;\n- i2c->sts = 0x00;\n- i2c->extsts = 0x00;\n- i2c->clkdiv = 0x00;\n- i2c->xfrcnt = 0x00;\n- i2c->directcntl = 0x0F;\n-}\n-\n-static void ppc405_i2c_init(hwaddr base, qemu_irq irq)\n-{\n- ppc4xx_i2c_t *i2c;\n-\n- i2c = g_malloc0(sizeof(ppc4xx_i2c_t));\n- i2c->irq = irq;\n-#ifdef DEBUG_I2C\n- printf(\"%s: offset \" TARGET_FMT_plx \"\\n\", __func__, base);\n-#endif\n- memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, \"i2c\", 0x011);\n- memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);\n- qemu_register_reset(ppc4xx_i2c_reset, i2c);\n-}\n-\n-/*****************************************************************************/\n /* General purpose timers */\n typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;\n struct ppc4xx_gpt_t {\ndiff --git a/hw/ppc/ppc4xx_i2c.c b/hw/ppc/ppc4xx_i2c.c\nnew file mode 100644\nindex 0000000000..15f2dea69e\n--- /dev/null\n+++ b/hw/ppc/ppc4xx_i2c.c\n@@ -0,0 +1,272 @@\n+/*\n+ * PPC4xx I2C controller emulation\n+ *\n+ * Copyright (c) 2007 Jocelyn Mayer\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qapi/error.h\"\n+#include \"qemu-common.h\"\n+#include \"cpu.h\"\n+#include \"hw/hw.h\"\n+#include \"exec/address-spaces.h\"\n+#include \"hw/ppc/ppc.h\"\n+#include \"ppc405.h\"\n+\n+/*#define DEBUG_I2C*/\n+\n+typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;\n+struct ppc4xx_i2c_t {\n+ qemu_irq irq;\n+ MemoryRegion iomem;\n+ uint8_t mdata;\n+ uint8_t lmadr;\n+ uint8_t hmadr;\n+ uint8_t cntl;\n+ uint8_t mdcntl;\n+ uint8_t sts;\n+ uint8_t extsts;\n+ uint8_t sdata;\n+ uint8_t lsadr;\n+ uint8_t hsadr;\n+ uint8_t clkdiv;\n+ uint8_t intrmsk;\n+ uint8_t xfrcnt;\n+ uint8_t xtcntlss;\n+ uint8_t directcntl;\n+};\n+\n+static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr addr)\n+{\n+ ppc4xx_i2c_t *i2c;\n+ uint32_t ret;\n+\n+#ifdef DEBUG_I2C\n+ printf(\"%s: addr \" TARGET_FMT_plx \"\\n\", __func__, addr);\n+#endif\n+ i2c = opaque;\n+ switch (addr) {\n+ case 0x00:\n+ /*i2c_readbyte(&i2c->mdata);*/\n+ ret = i2c->mdata;\n+ break;\n+ case 0x02:\n+ ret = i2c->sdata;\n+ break;\n+ case 0x04:\n+ ret = i2c->lmadr;\n+ break;\n+ case 0x05:\n+ ret = i2c->hmadr;\n+ break;\n+ case 0x06:\n+ ret = i2c->cntl;\n+ break;\n+ case 0x07:\n+ ret = i2c->mdcntl;\n+ break;\n+ case 0x08:\n+ ret = i2c->sts;\n+ break;\n+ case 0x09:\n+ ret = i2c->extsts;\n+ break;\n+ case 0x0A:\n+ ret = i2c->lsadr;\n+ break;\n+ case 0x0B:\n+ ret = i2c->hsadr;\n+ break;\n+ case 0x0C:\n+ ret = i2c->clkdiv;\n+ break;\n+ case 0x0D:\n+ ret = i2c->intrmsk;\n+ break;\n+ case 0x0E:\n+ ret = i2c->xfrcnt;\n+ break;\n+ case 0x0F:\n+ ret = i2c->xtcntlss;\n+ break;\n+ case 0x10:\n+ ret = i2c->directcntl;\n+ break;\n+ default:\n+ ret = 0x00;\n+ break;\n+ }\n+#ifdef DEBUG_I2C\n+ printf(\"%s: addr \" TARGET_FMT_plx \" %02\" PRIx32 \"\\n\", __func__, addr, ret);\n+#endif\n+\n+ return ret;\n+}\n+\n+static void ppc4xx_i2c_writeb(void *opaque,\n+ hwaddr addr, uint32_t value)\n+{\n+ ppc4xx_i2c_t *i2c;\n+\n+#ifdef DEBUG_I2C\n+ printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx32 \"\\n\", __func__, addr,\n+ value);\n+#endif\n+ i2c = opaque;\n+ switch (addr) {\n+ case 0x00:\n+ i2c->mdata = value;\n+ /*i2c_sendbyte(&i2c->mdata);*/\n+ break;\n+ case 0x02:\n+ i2c->sdata = value;\n+ break;\n+ case 0x04:\n+ i2c->lmadr = value;\n+ break;\n+ case 0x05:\n+ i2c->hmadr = value;\n+ break;\n+ case 0x06:\n+ i2c->cntl = value;\n+ break;\n+ case 0x07:\n+ i2c->mdcntl = value & 0xDF;\n+ break;\n+ case 0x08:\n+ i2c->sts &= ~(value & 0x0A);\n+ break;\n+ case 0x09:\n+ i2c->extsts &= ~(value & 0x8F);\n+ break;\n+ case 0x0A:\n+ i2c->lsadr = value;\n+ break;\n+ case 0x0B:\n+ i2c->hsadr = value;\n+ break;\n+ case 0x0C:\n+ i2c->clkdiv = value;\n+ break;\n+ case 0x0D:\n+ i2c->intrmsk = value;\n+ break;\n+ case 0x0E:\n+ i2c->xfrcnt = value & 0x77;\n+ break;\n+ case 0x0F:\n+ i2c->xtcntlss = value;\n+ break;\n+ case 0x10:\n+ i2c->directcntl = value & 0x7;\n+ break;\n+ }\n+}\n+\n+static uint32_t ppc4xx_i2c_readw(void *opaque, hwaddr addr)\n+{\n+ uint32_t ret;\n+\n+#ifdef DEBUG_I2C\n+ printf(\"%s: addr \" TARGET_FMT_plx \"\\n\", __func__, addr);\n+#endif\n+ ret = ppc4xx_i2c_readb(opaque, addr) << 8;\n+ ret |= ppc4xx_i2c_readb(opaque, addr + 1);\n+\n+ return ret;\n+}\n+\n+static void ppc4xx_i2c_writew(void *opaque,\n+ hwaddr addr, uint32_t value)\n+{\n+#ifdef DEBUG_I2C\n+ printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx32 \"\\n\", __func__, addr,\n+ value);\n+#endif\n+ ppc4xx_i2c_writeb(opaque, addr, value >> 8);\n+ ppc4xx_i2c_writeb(opaque, addr + 1, value);\n+}\n+\n+static uint32_t ppc4xx_i2c_readl(void *opaque, hwaddr addr)\n+{\n+ uint32_t ret;\n+\n+#ifdef DEBUG_I2C\n+ printf(\"%s: addr \" TARGET_FMT_plx \"\\n\", __func__, addr);\n+#endif\n+ ret = ppc4xx_i2c_readb(opaque, addr) << 24;\n+ ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;\n+ ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;\n+ ret |= ppc4xx_i2c_readb(opaque, addr + 3);\n+\n+ return ret;\n+}\n+\n+static void ppc4xx_i2c_writel(void *opaque,\n+ hwaddr addr, uint32_t value)\n+{\n+#ifdef DEBUG_I2C\n+ printf(\"%s: addr \" TARGET_FMT_plx \" val %08\" PRIx32 \"\\n\", __func__, addr,\n+ value);\n+#endif\n+ ppc4xx_i2c_writeb(opaque, addr, value >> 24);\n+ ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);\n+ ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);\n+ ppc4xx_i2c_writeb(opaque, addr + 3, value);\n+}\n+\n+static const MemoryRegionOps i2c_ops = {\n+ .old_mmio = {\n+ .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },\n+ .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },\n+ },\n+ .endianness = DEVICE_NATIVE_ENDIAN,\n+};\n+\n+static void ppc4xx_i2c_reset(void *opaque)\n+{\n+ ppc4xx_i2c_t *i2c;\n+\n+ i2c = opaque;\n+ i2c->mdata = 0x00;\n+ i2c->sdata = 0x00;\n+ i2c->cntl = 0x00;\n+ i2c->mdcntl = 0x00;\n+ i2c->sts = 0x00;\n+ i2c->extsts = 0x00;\n+ i2c->clkdiv = 0x00;\n+ i2c->xfrcnt = 0x00;\n+ i2c->directcntl = 0x0F;\n+}\n+\n+void ppc405_i2c_init(hwaddr base, qemu_irq irq)\n+{\n+ ppc4xx_i2c_t *i2c;\n+\n+ i2c = g_malloc0(sizeof(ppc4xx_i2c_t));\n+ i2c->irq = irq;\n+#ifdef DEBUG_I2C\n+ printf(\"%s: offset \" TARGET_FMT_plx \"\\n\", __func__, base);\n+#endif\n+ memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, \"i2c\", 0x011);\n+ memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);\n+ qemu_register_reset(ppc4xx_i2c_reset, i2c);\n+}\n","prefixes":["PULL","24/40"]}