{"id":811507,"url":"http://patchwork.ozlabs.org/api/patches/811507/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-21-david@gibson.dropbear.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908103558.31632-21-david@gibson.dropbear.id.au>","list_archive_url":null,"date":"2017-09-08T10:35:38","name":"[PULL,20/40] ppc64: introduce e6500","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2f97ecae700b363cd7daa823b4c21d9787d2cbeb","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/?format=json","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-21-david@gibson.dropbear.id.au/mbox/","series":[{"id":2179,"url":"http://patchwork.ozlabs.org/api/series/2179/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2179","date":"2017-09-08T10:35:20","name":"[PULL,01/40] hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->dev","version":1,"mbox":"http://patchwork.ozlabs.org/series/2179/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811507/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811507/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"isMhIqb1\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpYs70gKBz9s3w\n\tfor ;\n\tFri, 8 Sep 2017 20:46:19 +1000 (AEST)","from localhost ([::1]:44496 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dqGnh-0002hm-2v\n\tfor incoming@patchwork.ozlabs.org; Fri, 08 Sep 2017 06:46:17 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:58708)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dqGe6-00029v-Ra\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:31 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dqGe0-0003FA-T8\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:22 -0400","from ozlabs.org ([2401:3900:2:1::2]:59749)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dqGdz-0003BI-FA; Fri, 08 Sep 2017 06:36:16 -0400","by ozlabs.org (Postfix, from userid 1007)\n\tid 3xpYdK2J0Pz9t3w; Fri, 8 Sep 2017 20:36:04 +1000 (AEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1504866965;\n\tbh=CU1BlHzc/lBE980DbHuRTfVd8Q1T+KcQEnInH5aGPZ0=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=isMhIqb1ArKeFluYPbLsTI9R6VIlHdIsI/8OqQ8QIQ2vHzjsN/x4CwZCGnVJKo+ax\n\tqTGkOpV/NHSSt+v63v4ZfAGpytE3MA+tu8W52F4EZEjvkU7FgU+kx4kXgDzWjkZgrU\n\tB14fA7TJ3FJ/yDKsOr7/iPBzEVJzsQvrX87YN4wc=","From":"David Gibson ","To":"peter.maydell@linaro.org","Date":"Fri, 8 Sep 2017 20:35:38 +1000","Message-Id":"<20170908103558.31632-21-david@gibson.dropbear.id.au>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170908103558.31632-1-david@gibson.dropbear.id.au>","References":"<20170908103558.31632-1-david@gibson.dropbear.id.au>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2401:3900:2:1::2","Subject":"[Qemu-devel] [PULL 20/40] ppc64: introduce e6500","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de,\n\tmdroth@linux.vnet.ibm.com,\n\tKONRAD Frederic , \n\tqemu-ppc@nongnu.org, imammedo@redhat.com, sam.bobroff@au1.ibm.com,\n\tDavid Gibson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: KONRAD Frederic \n\nThis introduces e6500 core.\n\nSigned-off-by: KONRAD Frederic \nSigned-off-by: David Gibson \n---\n target/ppc/cpu-models.c | 2 +\n target/ppc/cpu-models.h | 1 +\n target/ppc/translate_init.c | 91 ++++++++++++++++++++++++++++++++++++++++++++-\n 3 files changed, 93 insertions(+), 1 deletion(-)","diff":"diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c\nindex 4d3e6354cf..e0d9faf848 100644\n--- a/target/ppc/cpu-models.c\n+++ b/target/ppc/cpu-models.c\n@@ -693,6 +693,8 @@\n #ifdef TARGET_PPC64\n POWERPC_DEF_SVR(\"e5500\", \"e5500\",\n CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)\n+ POWERPC_DEF_SVR(\"e6500\", \"e6500\",\n+ CPU_POWERPC_e6500, POWERPC_SVR_E500, e6500)\n #endif\n /* PowerPC e500 microcontrollers */\n POWERPC_DEF_SVR(\"MPC8533_v10\", \"MPC8533 v1.0\",\ndiff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h\nindex b563c45b68..eaa6849a42 100644\n--- a/target/ppc/cpu-models.h\n+++ b/target/ppc/cpu-models.h\n@@ -346,6 +346,7 @@ enum {\n CPU_POWERPC_e500v2_v30 = 0x80210030,\n CPU_POWERPC_e500mc = 0x80230020,\n CPU_POWERPC_e5500 = 0x80240020,\n+ CPU_POWERPC_e6500 = 0x80400020,\n /* MPC85xx microcontrollers */\n #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21\n #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22\ndiff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c\nindex 4104629df7..08ef74f064 100644\n--- a/target/ppc/translate_init.c\n+++ b/target/ppc/translate_init.c\n@@ -4888,6 +4888,7 @@ enum fsl_e500_version {\n fsl_e500v2,\n fsl_e500mc,\n fsl_e5500,\n+ fsl_e6500,\n };\n \n static void init_proc_e500(CPUPPCState *env, int version)\n@@ -4922,6 +4923,9 @@ static void init_proc_e500(CPUPPCState *env, int version)\n case fsl_e5500:\n ivor_mask = 0x000003FE0000FFFFULL;\n break;\n+ case fsl_e6500:\n+ ivor_mask = 0x000003FF0000FFFFULL;\n+ break;\n }\n gen_spr_BookE(env, ivor_mask);\n gen_spr_usprg3(env);\n@@ -4954,6 +4958,12 @@ static void init_proc_e500(CPUPPCState *env, int version)\n tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);\n tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);\n break;\n+ case fsl_e6500:\n+ mmucfg = 0x6510B45;\n+ env->nb_pids = 1;\n+ tlbncfg[0] = 0x08052400;\n+ tlbncfg[1] = 0x40028040;\n+ break;\n default:\n cpu_abort(CPU(cpu), \"Unknown CPU: \" TARGET_FMT_lx \"\\n\", env->spr[SPR_PVR]);\n }\n@@ -4972,6 +4982,12 @@ static void init_proc_e500(CPUPPCState *env, int version)\n l1cfg0 |= 0x1000000; /* 64 byte cache block size */\n l1cfg1 |= 0x1000000; /* 64 byte cache block size */\n break;\n+ case fsl_e6500:\n+ env->dcache_line_size = 32;\n+ env->icache_line_size = 32;\n+ l1cfg0 |= 0x0F83820;\n+ l1cfg1 |= 0x0B83820;\n+ break;\n default:\n cpu_abort(CPU(cpu), \"Unknown CPU: \" TARGET_FMT_lx \"\\n\", env->spr[SPR_PVR]);\n }\n@@ -5050,7 +5066,7 @@ static void init_proc_e500(CPUPPCState *env, int version)\n &spr_read_generic, SPR_NOACCESS,\n 0x00000000);\n /* XXX better abstract into Emb.xxx features */\n- if (version == fsl_e5500) {\n+ if ((version == fsl_e5500) || (version == fsl_e6500)) {\n spr_register(env, SPR_BOOKE_EPCR, \"EPCR\",\n SPR_NOACCESS, SPR_NOACCESS,\n &spr_read_generic, &spr_write_generic,\n@@ -5062,6 +5078,30 @@ static void init_proc_e500(CPUPPCState *env, int version)\n ivpr_mask = (target_ulong)~0xFFFFULL;\n }\n \n+ if (version == fsl_e6500) {\n+ spr_register(env, SPR_BOOKE_SPRG8, \"SPRG8\",\n+ SPR_NOACCESS, SPR_NOACCESS,\n+ &spr_read_generic, &spr_write_generic,\n+ 0x00000000);\n+ spr_register(env, SPR_BOOKE_SPRG9, \"SPRG9\",\n+ SPR_NOACCESS, SPR_NOACCESS,\n+ &spr_read_generic, &spr_write_generic,\n+ 0x00000000);\n+ /* Thread identification */\n+ spr_register(env, SPR_TIR, \"TIR\",\n+ SPR_NOACCESS, SPR_NOACCESS,\n+ &spr_read_generic, SPR_NOACCESS,\n+ 0x00000000);\n+ spr_register(env, SPR_BOOKE_TLB0PS, \"TLB0PS\",\n+ SPR_NOACCESS, SPR_NOACCESS,\n+ &spr_read_generic, SPR_NOACCESS,\n+ 0x00000004);\n+ spr_register(env, SPR_BOOKE_TLB1PS, \"TLB1PS\",\n+ SPR_NOACCESS, SPR_NOACCESS,\n+ &spr_read_generic, SPR_NOACCESS,\n+ 0x7FFFFFFC);\n+ }\n+\n #if !defined(CONFIG_USER_ONLY)\n env->nb_tlb = 0;\n env->tlb_type = TLB_MAS;\n@@ -5254,6 +5294,55 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)\n pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |\n POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;\n }\n+\n+static void init_proc_e6500(CPUPPCState *env)\n+{\n+ init_proc_e500(env, fsl_e6500);\n+}\n+\n+POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(oc);\n+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);\n+\n+ dc->desc = \"e6500 core\";\n+ pcc->init_proc = init_proc_e6500;\n+ pcc->check_pow = check_pow_none;\n+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |\n+ PPC_WRTEE | PPC_RFDI | PPC_RFMCI |\n+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |\n+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |\n+ PPC_FLOAT | PPC_FLOAT_FRES |\n+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |\n+ PPC_FLOAT_STFIWX | PPC_WAIT |\n+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |\n+ PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;\n+ pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \\\n+ PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;\n+ pcc->msr_mask = (1ull << MSR_CM) |\n+ (1ull << MSR_GS) |\n+ (1ull << MSR_UCLE) |\n+ (1ull << MSR_CE) |\n+ (1ull << MSR_EE) |\n+ (1ull << MSR_PR) |\n+ (1ull << MSR_FP) |\n+ (1ull << MSR_ME) |\n+ (1ull << MSR_FE0) |\n+ (1ull << MSR_DE) |\n+ (1ull << MSR_FE1) |\n+ (1ull << MSR_IS) |\n+ (1ull << MSR_DS) |\n+ (1ull << MSR_PX) |\n+ (1ull << MSR_RI) |\n+ (1ull << MSR_VR);\n+ pcc->mmu_model = POWERPC_MMU_BOOKE206;\n+ pcc->excp_model = POWERPC_EXCP_BOOKE;\n+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;\n+ pcc->bfd_mach = bfd_mach_ppc_e500;\n+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |\n+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;\n+}\n+\n #endif\n \n /* Non-embedded PowerPC */\n","prefixes":["PULL","20/40"]}