{"id":811435,"url":"http://patchwork.ozlabs.org/api/patches/811435/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908095348.16578-5-thomas.petazzoni@free-electrons.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908095348.16578-5-thomas.petazzoni@free-electrons.com>","list_archive_url":null,"date":"2017-09-08T09:53:45","name":"[4/7] PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq mode","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"d9f85f4548781e0bb712d3eddd82723832a09396","submitter":{"id":2230,"url":"http://patchwork.ozlabs.org/api/people/2230/?format=json","name":"Thomas Petazzoni","email":"thomas.petazzoni@free-electrons.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908095348.16578-5-thomas.petazzoni@free-electrons.com/mbox/","series":[{"id":2162,"url":"http://patchwork.ozlabs.org/api/series/2162/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=2162","date":"2017-09-08T09:53:41","name":"PCI: aardvark: improve compatibility with PCI devices","version":1,"mbox":"http://patchwork.ozlabs.org/series/2162/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811435/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811435/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpXhy3N73z9s8J\n\tfor ;\n\tFri, 8 Sep 2017 19:54:10 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753292AbdIHJyJ (ORCPT );\n\tFri, 8 Sep 2017 05:54:09 -0400","from mail.free-electrons.com ([62.4.15.54]:41970 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753527AbdIHJyA (ORCPT\n\t); Fri, 8 Sep 2017 05:54:00 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 4BA4521D32; Fri, 8 Sep 2017 11:53:58 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 1CA5320A4E;\n\tFri, 8 Sep 2017 11:53:58 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","From":"Thomas Petazzoni ","To":"Bjorn Helgaas , linux-pci@vger.kernel.org","Cc":"Nadav Haklai , Hanna Hawa ,\n\tYehuda Yitschak , Victor Gu ,\n\tJason Cooper , Andrew Lunn ,\n\tSebastian Hesselbarth , Gregory Clement\n\t, \n\tlinux-arm-kernel@lists.infradead.org, =?utf-8?q?Miqu=C3=A8l_Raynal?=\n\t, Antoine Tenart\n\t, Thomas Petazzoni\n\t","Subject":"[PATCH 4/7] PCI: aardvark: use isr1 instead of isr0 interrupt in\n\tlegacy irq mode","Date":"Fri, 8 Sep 2017 11:53:45 +0200","Message-Id":"<20170908095348.16578-5-thomas.petazzoni@free-electrons.com>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170908095348.16578-1-thomas.petazzoni@free-electrons.com>","References":"<20170908095348.16578-1-thomas.petazzoni@free-electrons.com>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"From: Victor Gu \n\nThe Aardvark has two interrupts sets:\n\n - first set is bit[23:16] of PCIe ISR 0 register(RD0074840h)\n\n - second set is bit[11:8] of PCIe ISR 1 register(RD0074848h)\n\nOnly one set should be used, while another set should be masked.\n\nThe second set, ISR1, is more advanced, the Legacy INT_X status bit is\nasserted once Assert_INTX message is received, and de-asserted after\nDeassert_INTX message is received. Therefore, it matches what the\ndriver is currently doing in the ->irq_mask() and ->irq_unmask()\nfunctions. The ISR0 requires additional work to deassert the\ninterrupt, which the driver doesn't do currently.\n\nThis commit resolves a number of issues with legacy interrupts.\n\nThis is part of fixing bug\nhttps://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was\nreported as the user to be important to get a Intel 7260 mini-PCIe\nWiFi card working.\n\nFixes: 8c39d710363c1 (\"PCI: aardvark: Add Aardvark PCI host controller driver\")\nSigned-off-by: Victor Gu \nReviewed-by: Evan Wang \nReviewed-by: Nadav Haklai \n[Thomas: tweak commit log.]\nSigned-off-by: Thomas Petazzoni \n---\n drivers/pci/host/pci-aardvark.c | 41 ++++++++++++++++++++++++-----------------\n 1 file changed, 24 insertions(+), 17 deletions(-)","diff":"diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c\nindex e361c673732f..4a563d8526ae 100644\n--- a/drivers/pci/host/pci-aardvark.c\n+++ b/drivers/pci/host/pci-aardvark.c\n@@ -105,7 +105,8 @@\n #define PCIE_ISR1_MASK_REG\t\t\t(CONTROL_BASE_ADDR + 0x4C)\n #define PCIE_ISR1_POWER_STATE_CHANGE\tBIT(4)\n #define PCIE_ISR1_FLUSH\t\t\tBIT(5)\n-#define PCIE_ISR1_ALL_MASK\t\t\tGENMASK(5, 4)\n+#define PCIE_ISR1_INTX_ASSERT(val)\t\tBIT(8 + (val))\n+#define PCIE_ISR1_ALL_MASK\t\t\tGENMASK(11, 4)\n #define PCIE_MSI_ADDR_LOW_REG\t\t\t(CONTROL_BASE_ADDR + 0x50)\n #define PCIE_MSI_ADDR_HIGH_REG\t\t\t(CONTROL_BASE_ADDR + 0x54)\n #define PCIE_MSI_STATUS_REG\t\t\t(CONTROL_BASE_ADDR + 0x58)\n@@ -616,9 +617,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)\n \tirq_hw_number_t hwirq = irqd_to_hwirq(d);\n \tu32 mask;\n \n-\tmask = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n-\tmask |= PCIE_ISR0_INTX_ASSERT(hwirq);\n-\tadvk_writel(pcie, mask, PCIE_ISR0_MASK_REG);\n+\tmask = advk_readl(pcie, PCIE_ISR1_MASK_REG);\n+\tmask |= PCIE_ISR1_INTX_ASSERT(hwirq);\n+\tadvk_writel(pcie, mask, PCIE_ISR1_MASK_REG);\n }\n \n static void advk_pcie_irq_unmask(struct irq_data *d)\n@@ -627,9 +628,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)\n \tirq_hw_number_t hwirq = irqd_to_hwirq(d);\n \tu32 mask;\n \n-\tmask = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n-\tmask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);\n-\tadvk_writel(pcie, mask, PCIE_ISR0_MASK_REG);\n+\tmask = advk_readl(pcie, PCIE_ISR1_MASK_REG);\n+\tmask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);\n+\tadvk_writel(pcie, mask, PCIE_ISR1_MASK_REG);\n }\n \n static int advk_pcie_irq_map(struct irq_domain *h,\n@@ -772,29 +773,35 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)\n \n static void advk_pcie_handle_int(struct advk_pcie *pcie)\n {\n-\tu32 val, mask, status;\n+\tu32 isr0_val, isr0_mask, isr0_status;\n+\tu32 isr1_val, isr1_mask, isr1_status;\n \tint i, virq;\n \n-\tval = advk_readl(pcie, PCIE_ISR0_REG);\n-\tmask = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n-\tstatus = val & ((~mask) & PCIE_ISR0_ALL_MASK);\n+\tisr0_val = advk_readl(pcie, PCIE_ISR0_REG);\n+\tisr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n+\tisr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);\n \n-\tif (!status) {\n-\t\tadvk_writel(pcie, val, PCIE_ISR0_REG);\n+\tisr1_val = advk_readl(pcie, PCIE_ISR1_REG);\n+\tisr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);\n+\tisr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);\n+\n+\tif (!isr0_status && !isr1_status) {\n+\t\tadvk_writel(pcie, isr0_val, PCIE_ISR0_REG);\n+\t\tadvk_writel(pcie, isr1_val, PCIE_ISR1_REG);\n \t\treturn;\n \t}\n \n \t/* Process MSI interrupts */\n-\tif (status & PCIE_ISR0_MSI_INT_PENDING)\n+\tif (isr0_status & PCIE_ISR0_MSI_INT_PENDING)\n \t\tadvk_pcie_handle_msi(pcie);\n \n \t/* Process legacy interrupts */\n \tfor (i = 0; i < LEGACY_IRQ_NUM; i++) {\n-\t\tif (!(status & PCIE_ISR0_INTX_ASSERT(i)))\n+\t\tif (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))\n \t\t\tcontinue;\n \n-\t\tadvk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),\n-\t\t\t PCIE_ISR0_REG);\n+\t\tadvk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),\n+\t\t\t PCIE_ISR1_REG);\n \n \t\tvirq = irq_find_mapping(pcie->irq_domain, i);\n \t\tgeneric_handle_irq(virq);\n","prefixes":["4/7"]}