{"id":811433,"url":"http://patchwork.ozlabs.org/api/patches/811433/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908095348.16578-7-thomas.petazzoni@free-electrons.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908095348.16578-7-thomas.petazzoni@free-electrons.com>","list_archive_url":null,"date":"2017-09-08T09:53:47","name":"[6/7] PCI: aardvark: fix PCIe max read request size setting","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"172713aa9b4a3457c502f8cd28554245ba27a77c","submitter":{"id":2230,"url":"http://patchwork.ozlabs.org/api/people/2230/?format=json","name":"Thomas Petazzoni","email":"thomas.petazzoni@free-electrons.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908095348.16578-7-thomas.petazzoni@free-electrons.com/mbox/","series":[{"id":2162,"url":"http://patchwork.ozlabs.org/api/series/2162/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=2162","date":"2017-09-08T09:53:41","name":"PCI: aardvark: improve compatibility with PCI devices","version":1,"mbox":"http://patchwork.ozlabs.org/series/2162/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811433/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811433/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpXhx20pYz9sQl\n\tfor ;\n\tFri, 8 Sep 2017 19:54:09 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753442AbdIHJyG (ORCPT );\n\tFri, 8 Sep 2017 05:54:06 -0400","from mail.free-electrons.com ([62.4.15.54]:41977 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752872AbdIHJyB (ORCPT\n\t); Fri, 8 Sep 2017 05:54:01 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid E69B921D35; Fri, 8 Sep 2017 11:53:58 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id B96BC20A4E;\n\tFri, 8 Sep 2017 11:53:58 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","From":"Thomas Petazzoni ","To":"Bjorn Helgaas , linux-pci@vger.kernel.org","Cc":"Nadav Haklai , Hanna Hawa ,\n\tYehuda Yitschak , Victor Gu ,\n\tJason Cooper , Andrew Lunn ,\n\tSebastian Hesselbarth , Gregory Clement\n\t, \n\tlinux-arm-kernel@lists.infradead.org, =?utf-8?q?Miqu=C3=A8l_Raynal?=\n\t, Antoine Tenart\n\t, Evan Wang ,\n\tThomas Petazzoni ","Subject":"[PATCH 6/7] PCI: aardvark: fix PCIe max read request size setting","Date":"Fri, 8 Sep 2017 11:53:47 +0200","Message-Id":"<20170908095348.16578-7-thomas.petazzoni@free-electrons.com>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170908095348.16578-1-thomas.petazzoni@free-electrons.com>","References":"<20170908095348.16578-1-thomas.petazzoni@free-electrons.com>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"From: Evan Wang \n\nThere is an obvious typo issue in the definition of the PCIe maximum\nread request size: a bit shift is directly used as a value, while it\nshould be used to shift the correct value.\n\nThis is part of fixing bug\nhttps://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was\nreported as the user to be important to get a Intel 7260 mini-PCIe\nWiFi card working.\n\nFixes: 8c39d710363c1 (\"PCI: aardvark: Add Aardvark PCI host controller driver\")\nSigned-off-by: Evan Wang \nReviewed-by: Victor Gu \nReviewed-by: Nadav Haklai \n[Thomas: tweak commit log.]\nSigned-off-by: Thomas Petazzoni \n---\n drivers/pci/host/pci-aardvark.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c\nindex 461517a87eca..6d6a2ae35481 100644\n--- a/drivers/pci/host/pci-aardvark.c\n+++ b/drivers/pci/host/pci-aardvark.c\n@@ -33,6 +33,7 @@\n #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ\t\t0x2\n #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE\t\t(0 << 11)\n #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT\t12\n+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ\t\t0x2\n #define PCIE_CORE_MPS_UNIT_BYTE\t\t\t\t128\n #define PCIE_CORE_LINK_CTRL_STAT_REG\t\t\t\t0xd0\n #define PCIE_CORE_LINK_L0S_ENTRY\t\t\t\tBIT(0)\n@@ -304,7 +305,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)\n \t\t(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<\n \t\t PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |\n \t\tPCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |\n-\t\tPCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;\n+\t\t(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<\n+\t\t PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);\n \tadvk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);\n \n \t/* Program PCIe Control 2 to disable strict ordering */\n","prefixes":["6/7"]}