{"id":811379,"url":"http://patchwork.ozlabs.org/api/patches/811379/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908081033.3025-2-jglauber@cavium.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908081033.3025-2-jglauber@cavium.com>","list_archive_url":null,"date":"2017-09-08T08:10:31","name":"[v4,1/3] PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"65c8c059234e4a22d2dacaeab8f51002b7d9cb53","submitter":{"id":68350,"url":"http://patchwork.ozlabs.org/api/people/68350/?format=json","name":"Jan Glauber","email":"jglauber@cavium.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908081033.3025-2-jglauber@cavium.com/mbox/","series":[{"id":2127,"url":"http://patchwork.ozlabs.org/api/series/2127/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=2127","date":"2017-09-08T08:10:30","name":"Workaround for bus/slot reset on Cavium cn8xxx root ports","version":4,"mbox":"http://patchwork.ozlabs.org/series/2127/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811379/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811379/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpVSX1FMcz9s7p\n\tfor ;\n\tFri, 8 Sep 2017 18:13:16 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755896AbdIHIML (ORCPT );\n\tFri, 8 Sep 2017 04:12:11 -0400","from mail-wr0-f194.google.com ([209.85.128.194]:37468 \"EHLO\n\tmail-wr0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754719AbdIHIKy (ORCPT\n\t); Fri, 8 Sep 2017 04:10:54 -0400","by mail-wr0-f194.google.com with SMTP id u48so882589wrf.4;\n\tFri, 08 Sep 2017 01:10:53 -0700 (PDT)","from hc.fritz.box\n\t(HSI-KBW-46-223-156-13.hsi.kabel-badenwuerttemberg.de.\n\t[46.223.156.13]) by smtp.gmail.com with ESMTPSA id\n\tr14sm1600805wra.97.2017.09.08.01.10.52\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tFri, 08 Sep 2017 01:10:52 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=LJlmsNjACefTQD5KOQop3axr1AWO5Y9U01TlXydabkU=;\n\tb=lpnM+jHJL0jwDmWhDXxSaaKh1AJNloxFuLXy5eiWrufnCQlb0RO6EETdH92Cw+1hc2\n\t/PctHgrnZ8I5n//Pp2diMQzPK2f5QYz26tQLK17+quo3ZL+OlabfGW6RVBxBStr2AgLo\n\tW7YNP0dytG7wlu0cjT6jrztheoHfFZyOUiPCvAgSnYW1pjmeH3svotTfbeqIoXgqOVok\n\t7T8qye21xXJXNyRNA5JgxEPza7Mx5chhjM44tJaEKN9OcLqpr53ykRT2E8SyTxTpxLiH\n\tbpzYVzNajTKfup2y4gbWavmjY9RPxCf8jtK4UmYRtAe77hKC0MtIVcbRjB2RcFDkqNW1\n\tHuLQ==","X-Gm-Message-State":"AHPjjUjkhKluYP0D6LRKlEPCATK7WrW0jPArqMAjDp5hkLJrgCl16X9l\n\tT3V8RCxU0Qbn7A==","X-Google-Smtp-Source":"ADKCNb6GoTH1khXDfFBB/lBklpbC3toAUE49YaeffUzTh8m17epgjc6u3FyAHC1E3flI+m1fhMPeJQ==","X-Received":"by 10.223.172.66 with SMTP id v60mr1327313wrc.143.1504858253288; \n\tFri, 08 Sep 2017 01:10:53 -0700 (PDT)","From":"Jan Glauber ","To":"Bjorn Helgaas ","Cc":"linux-pci@vger.kernel.org, Alex Williamson ,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,\n\tJan Glauber ","Subject":"[PATCH v4 1/3] PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on\n\tbus device","Date":"Fri, 8 Sep 2017 10:10:31 +0200","Message-Id":"<20170908081033.3025-2-jglauber@cavium.com>","X-Mailer":"git-send-email 2.9.0.rc0.21.g7777322","In-Reply-To":"<20170908081033.3025-1-jglauber@cavium.com>","References":"<20170908081033.3025-1-jglauber@cavium.com>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"From: David Daney \n\nWhen checking to see if a PCI bus can safely be reset, we check to see\nif any of the children have their PCI_DEV_FLAGS_NO_BUS_RESET flag set.\nAs these devices are known not to behave well after a bus reset.\n\nSome PCIe root port bridges also do not behave well after a bus reset,\nsometimes causing the devices behind the bridge to become unusable.\n\nAdd a check for the PCI_DEV_FLAGS_NO_BUS_RESET flag being set in the\nbridge device to allow these bridges to be flagged, and prevent their\nbuses from being reset.\n\nA follow on patch will add a quirk for this type of bridge.\n\nSigned-off-by: David Daney \n[jglauber@cavium.com: fixed typo]\nSigned-off-by: Jan Glauber \n---\n drivers/pci/pci.c | 4 ++++\n 1 file changed, 4 insertions(+)","diff":"diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex fdf65a6c13f6..b2a46ca7f133 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -4325,6 +4325,10 @@ static bool pci_bus_resetable(struct pci_bus *bus)\n {\n \tstruct pci_dev *dev;\n \n+\n+\tif (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))\n+\t\treturn false;\n+\n \tlist_for_each_entry(dev, &bus->devices, bus_list) {\n \t\tif (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||\n \t\t (dev->subordinate && !pci_bus_resetable(dev->subordinate)))\n","prefixes":["v4","1/3"]}