{"id":811378,"url":"http://patchwork.ozlabs.org/api/patches/811378/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908081033.3025-3-jglauber@cavium.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908081033.3025-3-jglauber@cavium.com>","list_archive_url":null,"date":"2017-09-08T08:10:32","name":"[v4,2/3] PCI: Avoid bus reset for Cavium cn8xxx root ports","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"82123b16b8e2bd0f304bf9826c08fcd4da239bfe","submitter":{"id":68350,"url":"http://patchwork.ozlabs.org/api/people/68350/?format=json","name":"Jan Glauber","email":"jglauber@cavium.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908081033.3025-3-jglauber@cavium.com/mbox/","series":[{"id":2127,"url":"http://patchwork.ozlabs.org/api/series/2127/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=2127","date":"2017-09-08T08:10:30","name":"Workaround for bus/slot reset on Cavium cn8xxx root ports","version":4,"mbox":"http://patchwork.ozlabs.org/series/2127/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811378/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811378/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpVRL2sGpz9s7p\n\tfor ;\n\tFri, 8 Sep 2017 18:12:14 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754673AbdIHIML (ORCPT );\n\tFri, 8 Sep 2017 04:12:11 -0400","from mail-wr0-f195.google.com ([209.85.128.195]:37471 \"EHLO\n\tmail-wr0-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754695AbdIHIKz (ORCPT\n\t); Fri, 8 Sep 2017 04:10:55 -0400","by mail-wr0-f195.google.com with SMTP id u48so882604wrf.4;\n\tFri, 08 Sep 2017 01:10:54 -0700 (PDT)","from hc.fritz.box\n\t(HSI-KBW-46-223-156-13.hsi.kabel-badenwuerttemberg.de.\n\t[46.223.156.13]) by smtp.gmail.com with ESMTPSA id\n\tr14sm1600805wra.97.2017.09.08.01.10.53\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tFri, 08 Sep 2017 01:10:53 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=940pvKatQsf42PQwMuPv2jVqJA+Jza7dO3MorMrgRho=;\n\tb=txsVTuiDbvfdNs6e777mgYaO2BkD7vTQsmGYDiuFId2Bl6rpE2kdX4xK6/PITIGmwy\n\tNojIDOf5+Ijq7vOUAM63Q86YN8e+VI5S3sWJI0Vq1FWXECJVzJdkzaAg0zHmooqjXUla\n\t/4Vtg4i+wFJNPgj9Bm6mHal53M7Wxhc1L7GQ7oMsLYvORXmowChAUdMtGVyv097wg/nU\n\tqyyF+VYszDDEOHlBMwcZQPRlZ3w3MSYsZvmuKYX3R/GFWK/a2uMhtSAQVR/mavNG23NA\n\ti1WD1RWM9FAXjA6eWmqgSlGJFiKMvf8M3NBIXJRyNNnv0TT2IHSrKrYcT8CdJg6PbMCT\n\tHIUA==","X-Gm-Message-State":"AHPjjUg0fzLOVxvQ5/WUoFvVNgLe9znmp10J5Pt8S4pgGQyHIaFm2DWM\n\tjeMicDmNyQb9dQ==","X-Google-Smtp-Source":"ADKCNb60yaSb6bdG9q0Sx9lYWBybnMoxPKmuzrdf0ZZ4j1YYFayCMeXYxpjRg4HZcqBalPqUqWInGg==","X-Received":"by 10.223.184.122 with SMTP id u55mr1534049wrf.286.1504858254241;\n\tFri, 08 Sep 2017 01:10:54 -0700 (PDT)","From":"Jan Glauber ","To":"Bjorn Helgaas ","Cc":"linux-pci@vger.kernel.org, Alex Williamson ,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,\n\tJan Glauber ","Subject":"[PATCH v4 2/3] PCI: Avoid bus reset for Cavium cn8xxx root ports","Date":"Fri, 8 Sep 2017 10:10:32 +0200","Message-Id":"<20170908081033.3025-3-jglauber@cavium.com>","X-Mailer":"git-send-email 2.9.0.rc0.21.g7777322","In-Reply-To":"<20170908081033.3025-1-jglauber@cavium.com>","References":"<20170908081033.3025-1-jglauber@cavium.com>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"From: David Daney \n\nRoot ports of cn8xxx do not function after bus reset when used with\nsome e1000e and LSI HBA devices. Add a quirk to prevent bus reset on\nthese root ports.\n\nSigned-off-by: David Daney \n[jglauber@cavium.com: fixed typo and whitespaces]\nSigned-off-by: Jan Glauber \n---\n drivers/pci/quirks.c | 8 ++++++++\n 1 file changed, 8 insertions(+)","diff":"diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 140760403f36..2e4e7b6d1a79 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -3364,6 +3364,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);\n \n+/*\n+ * Root port on some Cavium CN8xxx chips do not successfully complete\n+ * a bus reset when used with certain types of child devices. Config\n+ * space access to the child may quit responding. Flag the root port\n+ * as not supporting bus reset.\n+ */\n+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);\n+\n static void quirk_no_pm_reset(struct pci_dev *dev)\n {\n \t/*\n","prefixes":["v4","2/3"]}