{"id":811376,"url":"http://patchwork.ozlabs.org/api/patches/811376/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908081033.3025-4-jglauber@cavium.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908081033.3025-4-jglauber@cavium.com>","list_archive_url":null,"date":"2017-09-08T08:10:33","name":"[v4,3/3] PCI: Avoid slot reset if bus reset is not possible","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"a572dd8035be604dd9468c86835c3d29b086fd02","submitter":{"id":68350,"url":"http://patchwork.ozlabs.org/api/people/68350/?format=json","name":"Jan Glauber","email":"jglauber@cavium.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170908081033.3025-4-jglauber@cavium.com/mbox/","series":[{"id":2127,"url":"http://patchwork.ozlabs.org/api/series/2127/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=2127","date":"2017-09-08T08:10:30","name":"Workaround for bus/slot reset on Cavium cn8xxx root ports","version":4,"mbox":"http://patchwork.ozlabs.org/series/2127/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811376/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811376/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpVQf2813z9s7p\n\tfor ;\n\tFri, 8 Sep 2017 18:11:38 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755545AbdIHILG (ORCPT );\n\tFri, 8 Sep 2017 04:11:06 -0400","from mail-wr0-f195.google.com ([209.85.128.195]:37475 \"EHLO\n\tmail-wr0-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754751AbdIHIK4 (ORCPT\n\t); Fri, 8 Sep 2017 04:10:56 -0400","by mail-wr0-f195.google.com with SMTP id u48so882619wrf.4;\n\tFri, 08 Sep 2017 01:10:55 -0700 (PDT)","from hc.fritz.box\n\t(HSI-KBW-46-223-156-13.hsi.kabel-badenwuerttemberg.de.\n\t[46.223.156.13]) by smtp.gmail.com with ESMTPSA id\n\tr14sm1600805wra.97.2017.09.08.01.10.54\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tFri, 08 Sep 2017 01:10:54 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=5OTDzmflPp/CT2VkRWR63Gn1g2nSBvk6jKRetKEFMEk=;\n\tb=sCJuiP6MpS/NbdGJ/bbfEaPc7dtWKMSWC45lbdLo2tNin/6ZFCHXRKLGa/xytSnlrE\n\tAZ+DzJkBDh54IAsdZ7YzVI1t/PdwvsKGgE85ABeRqqWmxeeS8f1Pz4wmSIGEqlsDZDCt\n\tP6WlTHTrwZV+3gSLbkUXdRiRsT0ZxIgJrK3IoFfaOu5BanoXprsx3Xt/SyC5x8a3dy8F\n\tQyIenrL+cTK0Ap4PY+BNW+A+xrT5Eg0vUEmr8LIMBEWBrMZ/7aoD31YovTl3K16d3t/s\n\t7vjx82lSw/QdqjpMnoy9C2qUlGeVO482zGPuz4m83WQTxj5q1YQGcGG+3ZtWarYY6xe5\n\tVVVw==","X-Gm-Message-State":"AHPjjUi1xPqYeYZ1AwbABeYsbF8ATVfXk8KlPy4oYHAOnjsPyQPXu98g\n\tJLyGJLIcB1ePig==","X-Google-Smtp-Source":"ADKCNb4fibfE2e+smADfbTGmDs5flxwuLfrydbez7375NSOgW+Svw5N/aEd9NLMdk9aVS/tIbtAELw==","X-Received":"by 10.223.164.13 with SMTP id d13mr1361346wra.48.1504858255146; \n\tFri, 08 Sep 2017 01:10:55 -0700 (PDT)","From":"Jan Glauber ","To":"Bjorn Helgaas ","Cc":"linux-pci@vger.kernel.org, Alex Williamson ,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,\n\tJan Glauber ","Subject":"[PATCH v4 3/3] PCI: Avoid slot reset if bus reset is not possible","Date":"Fri, 8 Sep 2017 10:10:33 +0200","Message-Id":"<20170908081033.3025-4-jglauber@cavium.com>","X-Mailer":"git-send-email 2.9.0.rc0.21.g7777322","In-Reply-To":"<20170908081033.3025-1-jglauber@cavium.com>","References":"<20170908081033.3025-1-jglauber@cavium.com>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"When checking to see if a PCI slot can safely be reset, we check to\nsee if any of the children have their PCI_DEV_FLAGS_NO_BUS_RESET flag\nset.\n\nSome PCIe root port bridges do not behave well after a slot reset,\nand may cause the device in the slot to become unusable.\n\nAdd a check for the PCI_DEV_FLAGS_NO_BUS_RESET flag being set in the\nbridge device to prevent the slot from being reset.\n\nSigned-off-by: Jan Glauber \n---\n drivers/pci/pci.c | 4 ++++\n 1 file changed, 4 insertions(+)","diff":"diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex b2a46ca7f133..45a086fc3592 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -4393,6 +4393,10 @@ static bool pci_slot_resetable(struct pci_slot *slot)\n {\n \tstruct pci_dev *dev;\n \n+\tif (slot->bus->self &&\n+\t (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))\n+\t\treturn false;\n+\n \tlist_for_each_entry(dev, &slot->bus->devices, bus_list) {\n \t\tif (!dev->slot || dev->slot != slot)\n \t\t\tcontinue;\n","prefixes":["v4","3/3"]}