{"id":811100,"url":"http://patchwork.ozlabs.org/api/patches/811100/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-3-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907181938.3948-3-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T18:19:36","name":"[PULL,2/4] target/alpha: Convert to DisasContextBase","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a6059807c6b187f1179ed855381e1cd8a44b5e64","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-3-richard.henderson@linaro.org/mbox/","series":[{"id":2035,"url":"http://patchwork.ozlabs.org/api/series/2035/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2035","date":"2017-09-07T18:19:34","name":"[PULL,1/4] target/alpha: Convert to DisasJumpType","version":1,"mbox":"http://patchwork.ozlabs.org/series/2035/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811100/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811100/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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-0700","Message-Id":"<20170907181938.3948-3-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170907181938.3948-1-richard.henderson@linaro.org>","References":"<20170907181938.3948-1-richard.henderson@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::230","Subject":"[Qemu-devel] [PULL 2/4] target/alpha: Convert to DisasContextBase","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, Richard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Richard Henderson \n\nSigned-off-by: Richard Henderson \n---\n target/alpha/translate.c | 78 ++++++++++++++++++++++++------------------------\n 1 file changed, 39 insertions(+), 39 deletions(-)","diff":"diff --git a/target/alpha/translate.c b/target/alpha/translate.c\nindex a75bf5dd90..ba38717e0f 100644\n--- a/target/alpha/translate.c\n+++ b/target/alpha/translate.c\n@@ -43,8 +43,8 @@\n \n typedef struct DisasContext DisasContext;\n struct DisasContext {\n- struct TranslationBlock *tb;\n- uint64_t pc;\n+ DisasContextBase base;\n+\n #ifndef CONFIG_USER_ONLY\n uint64_t palbr;\n #endif\n@@ -68,8 +68,6 @@ struct DisasContext {\n TCGv sink;\n /* Temporary for immediate constants. */\n TCGv lit;\n-\n- bool singlestep_enabled;\n };\n \n /* Target-specific return values from translate_one, indicating the\n@@ -282,7 +280,7 @@ static void gen_excp_1(int exception, int error_code)\n \n static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code)\n {\n- tcg_gen_movi_i64(cpu_pc, ctx->pc);\n+ tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);\n gen_excp_1(exception, error_code);\n return DISAS_NORETURN;\n }\n@@ -463,8 +461,8 @@ static bool in_superpage(DisasContext *ctx, int64_t addr)\n \n static bool use_exit_tb(DisasContext *ctx)\n {\n- return ((ctx->tb->cflags & CF_LAST_IO)\n- || ctx->singlestep_enabled\n+ return ((ctx->base.tb->cflags & CF_LAST_IO)\n+ || ctx->base.singlestep_enabled\n || singlestep);\n }\n \n@@ -480,7 +478,7 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t dest)\n return true;\n }\n /* Check for the dest on the same page as the start of the TB. */\n- return ((ctx->tb->pc ^ dest) & TARGET_PAGE_MASK) == 0;\n+ return ((ctx->base.tb->pc ^ dest) & TARGET_PAGE_MASK) == 0;\n #else\n return true;\n #endif\n@@ -488,10 +486,10 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t dest)\n \n static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp)\n {\n- uint64_t dest = ctx->pc + (disp << 2);\n+ uint64_t dest = ctx->base.pc_next + (disp << 2);\n \n if (ra != 31) {\n- tcg_gen_movi_i64(ctx->ir[ra], ctx->pc);\n+ tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next);\n }\n \n /* Notice branch-to-next; used to initialize RA with the PC. */\n@@ -500,7 +498,7 @@ static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp)\n } else if (use_goto_tb(ctx, dest)) {\n tcg_gen_goto_tb(0);\n tcg_gen_movi_i64(cpu_pc, dest);\n- tcg_gen_exit_tb((uintptr_t)ctx->tb);\n+ tcg_gen_exit_tb((uintptr_t)ctx->base.tb);\n return DISAS_NORETURN;\n } else {\n tcg_gen_movi_i64(cpu_pc, dest);\n@@ -511,26 +509,26 @@ static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp)\n static DisasJumpType gen_bcond_internal(DisasContext *ctx, TCGCond cond,\n TCGv cmp, int32_t disp)\n {\n- uint64_t dest = ctx->pc + (disp << 2);\n+ uint64_t dest = ctx->base.pc_next + (disp << 2);\n TCGLabel *lab_true = gen_new_label();\n \n if (use_goto_tb(ctx, dest)) {\n tcg_gen_brcondi_i64(cond, cmp, 0, lab_true);\n \n tcg_gen_goto_tb(0);\n- tcg_gen_movi_i64(cpu_pc, ctx->pc);\n- tcg_gen_exit_tb((uintptr_t)ctx->tb);\n+ tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);\n+ tcg_gen_exit_tb((uintptr_t)ctx->base.tb);\n \n gen_set_label(lab_true);\n tcg_gen_goto_tb(1);\n tcg_gen_movi_i64(cpu_pc, dest);\n- tcg_gen_exit_tb((uintptr_t)ctx->tb + 1);\n+ tcg_gen_exit_tb((uintptr_t)ctx->base.tb + 1);\n \n return DISAS_NORETURN;\n } else {\n TCGv_i64 z = tcg_const_i64(0);\n TCGv_i64 d = tcg_const_i64(dest);\n- TCGv_i64 p = tcg_const_i64(ctx->pc);\n+ TCGv_i64 p = tcg_const_i64(ctx->base.pc_next);\n \n tcg_gen_movcond_i64(cond, cpu_pc, cmp, z, d, p);\n \n@@ -1210,7 +1208,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)\n }\n \n /* Allow interrupts to be recognized right away. */\n- tcg_gen_movi_i64(cpu_pc, ctx->pc);\n+ tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);\n return DISAS_PC_UPDATED_NOCHAIN;\n \n case 0x36:\n@@ -1260,7 +1258,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)\n #else\n {\n TCGv tmp = tcg_temp_new();\n- uint64_t exc_addr = ctx->pc;\n+ uint64_t exc_addr = ctx->base.pc_next;\n uint64_t entry = ctx->palbr;\n \n if (ctx->tbflags & ENV_FLAG_PAL_MODE) {\n@@ -1285,7 +1283,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)\n if (!use_exit_tb(ctx)) {\n tcg_gen_goto_tb(0);\n tcg_gen_movi_i64(cpu_pc, entry);\n- tcg_gen_exit_tb((uintptr_t)ctx->tb);\n+ tcg_gen_exit_tb((uintptr_t)ctx->base.tb);\n return DISAS_NORETURN;\n } else {\n tcg_gen_movi_i64(cpu_pc, entry);\n@@ -2407,7 +2405,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)\n case 0xC000:\n /* RPCC */\n va = dest_gpr(ctx, ra);\n- if (ctx->tb->cflags & CF_USE_ICOUNT) {\n+ if (ctx->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n gen_helper_load_pcc(va, cpu_env);\n gen_io_end();\n@@ -2457,7 +2455,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)\n vb = load_gpr(ctx, rb);\n tcg_gen_andi_i64(cpu_pc, vb, ~3);\n if (ra != 31) {\n- tcg_gen_movi_i64(ctx->ir[ra], ctx->pc);\n+ tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next);\n }\n ret = DISAS_PC_UPDATED;\n break;\n@@ -2944,13 +2942,14 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n \n pc_start = tb->pc;\n \n- ctx.tb = tb;\n- ctx.pc = pc_start;\n+ ctx.base.tb = tb;\n+ ctx.base.pc_next = pc_start;\n+ ctx.base.singlestep_enabled = cs->singlestep_enabled;\n+\n ctx.tbflags = tb->flags;\n ctx.mem_idx = cpu_mmu_index(env, false);\n ctx.implver = env->implver;\n ctx.amask = env->amask;\n- ctx.singlestep_enabled = cs->singlestep_enabled;\n \n #ifdef CONFIG_USER_ONLY\n ctx.ir = cpu_std_ir;\n@@ -2992,39 +2991,40 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n tcg_clear_temp_count();\n \n do {\n- tcg_gen_insn_start(ctx.pc);\n+ tcg_gen_insn_start(ctx.base.pc_next);\n num_insns++;\n \n- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {\n+ if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {\n ret = gen_excp(&ctx, EXCP_DEBUG, 0);\n /* The address covered by the breakpoint must be included in\n [tb->pc, tb->pc + tb->size) in order to for it to be\n properly cleared -- thus we increment the PC here so that\n the logic setting tb->size below does the right thing. */\n- ctx.pc += 4;\n+ ctx.base.pc_next += 4;\n break;\n }\n if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n gen_io_start();\n }\n- insn = cpu_ldl_code(env, ctx.pc);\n+ insn = cpu_ldl_code(env, ctx.base.pc_next);\n \n- ctx.pc += 4;\n+ ctx.base.pc_next += 4;\n ret = translate_one(ctxp, insn);\n free_context_temps(ctxp);\n \n if (tcg_check_temp_count()) {\n- qemu_log(\"TCG temporary leak before \"TARGET_FMT_lx\"\\n\", ctx.pc);\n+ qemu_log(\"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n+ ctx.base.pc_next);\n }\n \n /* If we reach a page boundary, are single stepping,\n or exhaust instruction count, stop generation. */\n if (ret == DISAS_NEXT\n- && ((ctx.pc & pc_mask) == 0\n+ && ((ctx.base.pc_next & pc_mask) == 0\n || tcg_op_buf_full()\n || num_insns >= max_insns\n || singlestep\n- || ctx.singlestep_enabled)) {\n+ || ctx.base.singlestep_enabled)) {\n ret = DISAS_TOO_MANY;\n }\n } while (ret == DISAS_NEXT);\n@@ -3037,14 +3037,14 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n case DISAS_NORETURN:\n break;\n case DISAS_TOO_MANY:\n- if (use_goto_tb(&ctx, ctx.pc)) {\n+ if (use_goto_tb(&ctx, ctx.base.pc_next)) {\n tcg_gen_goto_tb(0);\n- tcg_gen_movi_i64(cpu_pc, ctx.pc);\n- tcg_gen_exit_tb((uintptr_t)ctx.tb);\n+ tcg_gen_movi_i64(cpu_pc, ctx.base.pc_next);\n+ tcg_gen_exit_tb((uintptr_t)ctx.base.tb);\n }\n /* FALLTHRU */\n case DISAS_PC_STALE:\n- tcg_gen_movi_i64(cpu_pc, ctx.pc);\n+ tcg_gen_movi_i64(cpu_pc, ctx.base.pc_next);\n /* FALLTHRU */\n case DISAS_PC_UPDATED:\n if (!use_exit_tb(&ctx)) {\n@@ -3053,7 +3053,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n }\n /* FALLTHRU */\n case DISAS_PC_UPDATED_NOCHAIN:\n- if (ctx.singlestep_enabled) {\n+ if (ctx.base.singlestep_enabled) {\n gen_excp_1(EXCP_DEBUG, 0);\n } else {\n tcg_gen_exit_tb(0);\n@@ -3065,7 +3065,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n \n gen_tb_end(tb, num_insns);\n \n- tb->size = ctx.pc - pc_start;\n+ tb->size = ctx.base.pc_next - pc_start;\n tb->icount = num_insns;\n \n #ifdef DEBUG_DISAS\n@@ -3073,7 +3073,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n && qemu_log_in_addr_range(pc_start)) {\n qemu_log_lock();\n qemu_log(\"IN: %s\\n\", lookup_symbol(pc_start));\n- log_target_disas(cs, pc_start, ctx.pc - pc_start, 1);\n+ log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start, 1);\n qemu_log(\"\\n\");\n qemu_log_unlock();\n }\n","prefixes":["PULL","2/4"]}