{"id":811099,"url":"http://patchwork.ozlabs.org/api/patches/811099/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-5-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907181938.3948-5-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T18:19:38","name":"[PULL,4/4] target/alpha: Switch to do_transaction_failed() hook","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ee08816c2c9faac6fbc529605eb806e4356d3701","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-5-richard.henderson@linaro.org/mbox/","series":[{"id":2035,"url":"http://patchwork.ozlabs.org/api/series/2035/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2035","date":"2017-09-07T18:19:34","name":"[PULL,1/4] target/alpha: Convert to DisasJumpType","version":1,"mbox":"http://patchwork.ozlabs.org/series/2035/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811099/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811099/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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This allows us to\nresolve a ??? in the old hook implementation.\n\nThe only part of the alpha target that does physical\nmemory accesses is reading the page table -- add a\nTODO comment there to the effect that we should handle\nbus faults on page table walks. (Since the palcode\ndoesn't actually do anything useful on a bus fault anyway\nit's a bit moot for now.)\n\nSigned-off-by: Peter Maydell \nMessage-Id: <1502196172-13818-1-git-send-email-peter.maydell@linaro.org>\nSigned-off-by: Richard Henderson \n---\n target/alpha/cpu.c | 2 +-\n target/alpha/cpu.h | 8 +++++---\n target/alpha/helper.c | 8 ++++++++\n target/alpha/mem_helper.c | 19 ++++++++++---------\n 4 files changed, 24 insertions(+), 13 deletions(-)","diff":"diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c\nindex 1ea597b9dd..e6c6aabdf0 100644\n--- a/target/alpha/cpu.c\n+++ b/target/alpha/cpu.c\n@@ -297,7 +297,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)\n #ifdef CONFIG_USER_ONLY\n cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;\n #else\n- cc->do_unassigned_access = alpha_cpu_unassigned_access;\n+ cc->do_transaction_failed = alpha_cpu_do_transaction_failed;\n cc->do_unaligned_access = alpha_cpu_do_unaligned_access;\n cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;\n dc->vmsd = &vmstate_alpha_cpu;\ndiff --git a/target/alpha/cpu.h b/target/alpha/cpu.h\nindex 0738e97d6d..6ae240969b 100644\n--- a/target/alpha/cpu.h\n+++ b/target/alpha/cpu.h\n@@ -486,9 +486,11 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);\n uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);\n void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);\n #ifndef CONFIG_USER_ONLY\n-QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,\n- bool is_write, bool is_exec,\n- int unused, unsigned size);\n+void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,\n+ vaddr addr, unsigned size,\n+ MMUAccessType access_type,\n+ int mmu_idx, MemTxAttrs attrs,\n+ MemTxResult response, uintptr_t retaddr);\n #endif\n \n static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,\ndiff --git a/target/alpha/helper.c b/target/alpha/helper.c\nindex 34121f4cad..36407f77f5 100644\n--- a/target/alpha/helper.c\n+++ b/target/alpha/helper.c\n@@ -163,6 +163,14 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,\n \n pt = env->ptbr;\n \n+ /* TODO: rather than using ldq_phys() to read the page table we should\n+ * use address_space_ldq() so that we can handle the case when\n+ * the page table read gives a bus fault, rather than ignoring it.\n+ * For the existing code the zero data that ldq_phys will return for\n+ * an access to invalid memory will result in our treating the page\n+ * table as invalid, which may even be the right behaviour.\n+ */\n+\n /* L1 page table read. */\n index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff;\n L1pte = ldq_phys(cs->as, pt + index*8);\ndiff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c\nindex 78a7d45590..3c06baa93a 100644\n--- a/target/alpha/mem_helper.c\n+++ b/target/alpha/mem_helper.c\n@@ -49,22 +49,23 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,\n cpu_loop_exit(cs);\n }\n \n-void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,\n- bool is_write, bool is_exec, int unused,\n- unsigned size)\n+void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,\n+ vaddr addr, unsigned size,\n+ MMUAccessType access_type,\n+ int mmu_idx, MemTxAttrs attrs,\n+ MemTxResult response, uintptr_t retaddr)\n {\n AlphaCPU *cpu = ALPHA_CPU(cs);\n CPUAlphaState *env = &cpu->env;\n \n+ if (retaddr) {\n+ cpu_restore_state(cs, retaddr);\n+ }\n+\n env->trap_arg0 = addr;\n- env->trap_arg1 = is_write ? 1 : 0;\n+ env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0;\n cs->exception_index = EXCP_MCHK;\n env->error_code = 0;\n-\n- /* ??? We should cpu_restore_state to the faulting insn, but this hook\n- does not have access to the retaddr value from the original helper.\n- It's all moot until the QEMU PALcode grows an MCHK handler. */\n-\n cpu_loop_exit(cs);\n }\n \n","prefixes":["PULL","4/4"]}