{"id":811096,"url":"http://patchwork.ozlabs.org/api/patches/811096/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-4-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907181938.3948-4-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T18:19:37","name":"[PULL,3/4] target/alpha: Convert to TranslatorOps","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"cd3e9dfddc36a62a8a27eb3d0f463f8af5c23fde","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-4-richard.henderson@linaro.org/mbox/","series":[{"id":2035,"url":"http://patchwork.ozlabs.org/api/series/2035/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2035","date":"2017-09-07T18:19:34","name":"[PULL,1/4] target/alpha: Convert to DisasJumpType","version":1,"mbox":"http://patchwork.ozlabs.org/series/2035/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811096/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811096/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Every TB begins with unset rounding mode, to be initialized on\n@@ -2964,96 +2954,87 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n to reset the FP_STATUS to that default at the end of any TB that\n changes the default. We could even (gasp) dynamiclly figure out\n what default would be most efficient given the running program. */\n- ctx.tb_rm = -1;\n+ ctx->tb_rm = -1;\n /* Similarly for flush-to-zero. */\n- ctx.tb_ftz = -1;\n+ ctx->tb_ftz = -1;\n \n- TCGV_UNUSED_I64(ctx.zero);\n- TCGV_UNUSED_I64(ctx.sink);\n- TCGV_UNUSED_I64(ctx.lit);\n-\n- num_insns = 0;\n- max_insns = tb->cflags & CF_COUNT_MASK;\n- if (max_insns == 0) {\n- max_insns = CF_COUNT_MASK;\n- }\n- if (max_insns > TCG_MAX_INSNS) {\n- max_insns = TCG_MAX_INSNS;\n- }\n+ TCGV_UNUSED_I64(ctx->zero);\n+ TCGV_UNUSED_I64(ctx->sink);\n+ TCGV_UNUSED_I64(ctx->lit);\n \n- if (in_superpage(&ctx, pc_start)) {\n- pc_mask = (1ULL << 41) - 1;\n+ /* Bound the number of insns to execute to those left on the page. */\n+ if (in_superpage(ctx, ctx->base.pc_first)) {\n+ mask = -1ULL << 41;\n } else {\n- pc_mask = ~TARGET_PAGE_MASK;\n+ mask = TARGET_PAGE_MASK;\n }\n+ bound = -(ctx->base.pc_first | mask) / 4;\n \n- gen_tb_start(tb);\n- tcg_clear_temp_count();\n+ return MIN(max_insns, bound);\n+}\n \n- do {\n- tcg_gen_insn_start(ctx.base.pc_next);\n- num_insns++;\n+static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n+{\n+}\n \n- if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {\n- ret = gen_excp(&ctx, EXCP_DEBUG, 0);\n- /* The address covered by the breakpoint must be included in\n- [tb->pc, tb->pc + tb->size) in order to for it to be\n- properly cleared -- thus we increment the PC here so that\n- the logic setting tb->size below does the right thing. */\n- ctx.base.pc_next += 4;\n- break;\n- }\n- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n- gen_io_start();\n- }\n- insn = cpu_ldl_code(env, ctx.base.pc_next);\n+static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ tcg_gen_insn_start(dcbase->pc_next);\n+}\n \n- ctx.base.pc_next += 4;\n- ret = translate_one(ctxp, insn);\n- free_context_temps(ctxp);\n+static bool alpha_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n+ const CPUBreakpoint *bp)\n+{\n+ DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n- if (tcg_check_temp_count()) {\n- qemu_log(\"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n- ctx.base.pc_next);\n- }\n+ ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG, 0);\n \n- /* If we reach a page boundary, are single stepping,\n- or exhaust instruction count, stop generation. */\n- if (ret == DISAS_NEXT\n- && ((ctx.base.pc_next & pc_mask) == 0\n- || tcg_op_buf_full()\n- || num_insns >= max_insns\n- || singlestep\n- || ctx.base.singlestep_enabled)) {\n- ret = DISAS_TOO_MANY;\n- }\n- } while (ret == DISAS_NEXT);\n+ /* The address covered by the breakpoint must be included in\n+ [tb->pc, tb->pc + tb->size) in order to for it to be\n+ properly cleared -- thus we increment the PC here so that\n+ the logic setting tb->size below does the right thing. */\n+ ctx->base.pc_next += 4;\n+ return true;\n+}\n \n- if (tb->cflags & CF_LAST_IO) {\n- gen_io_end();\n- }\n+static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *ctx = container_of(dcbase, DisasContext, base);\n+ CPUAlphaState *env = cpu->env_ptr;\n+ uint32_t insn = cpu_ldl_code(env, ctx->base.pc_next);\n+\n+ ctx->base.pc_next += 4;\n+ ctx->base.is_jmp = translate_one(ctx, insn);\n+\n+ free_context_temps(ctx);\n+ translator_loop_temp_check(&ctx->base);\n+}\n+\n+static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n- switch (ret) {\n+ switch (ctx->base.is_jmp) {\n case DISAS_NORETURN:\n break;\n case DISAS_TOO_MANY:\n- if (use_goto_tb(&ctx, ctx.base.pc_next)) {\n+ if (use_goto_tb(ctx, ctx->base.pc_next)) {\n tcg_gen_goto_tb(0);\n- tcg_gen_movi_i64(cpu_pc, ctx.base.pc_next);\n- tcg_gen_exit_tb((uintptr_t)ctx.base.tb);\n+ tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);\n+ tcg_gen_exit_tb((uintptr_t)ctx->base.tb);\n }\n /* FALLTHRU */\n case DISAS_PC_STALE:\n- tcg_gen_movi_i64(cpu_pc, ctx.base.pc_next);\n+ tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);\n /* FALLTHRU */\n case DISAS_PC_UPDATED:\n- if (!use_exit_tb(&ctx)) {\n+ if (!use_exit_tb(ctx)) {\n tcg_gen_lookup_and_goto_ptr(cpu_pc);\n break;\n }\n /* FALLTHRU */\n case DISAS_PC_UPDATED_NOCHAIN:\n- if (ctx.base.singlestep_enabled) {\n+ if (ctx->base.singlestep_enabled) {\n gen_excp_1(EXCP_DEBUG, 0);\n } else {\n tcg_gen_exit_tb(0);\n@@ -3062,22 +3043,28 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n default:\n g_assert_not_reached();\n }\n+}\n \n- gen_tb_end(tb, num_insns);\n-\n- tb->size = ctx.base.pc_next - pc_start;\n- tb->icount = num_insns;\n+static void alpha_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ qemu_log(\"IN: %s\\n\", lookup_symbol(dcbase->pc_first));\n+ log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size, 1);\n+}\n+\n+static const TranslatorOps alpha_tr_ops = {\n+ .init_disas_context = alpha_tr_init_disas_context,\n+ .tb_start = alpha_tr_tb_start,\n+ .insn_start = alpha_tr_insn_start,\n+ .breakpoint_check = alpha_tr_breakpoint_check,\n+ .translate_insn = alpha_tr_translate_insn,\n+ .tb_stop = alpha_tr_tb_stop,\n+ .disas_log = alpha_tr_disas_log,\n+};\n \n-#ifdef DEBUG_DISAS\n- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)\n- && qemu_log_in_addr_range(pc_start)) {\n- qemu_log_lock();\n- qemu_log(\"IN: %s\\n\", lookup_symbol(pc_start));\n- log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start, 1);\n- qemu_log(\"\\n\");\n- qemu_log_unlock();\n- }\n-#endif\n+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)\n+{\n+ DisasContext dc;\n+ translator_loop(&alpha_tr_ops, &dc.base, cpu, tb);\n }\n \n void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb,\n","prefixes":["PULL","3/4"]}