{"id":811063,"url":"http://patchwork.ozlabs.org/api/patches/811063/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170907145148.24398-5-npiggin@gmail.com/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<20170907145148.24398-5-npiggin@gmail.com>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/20170907145148.24398-5-npiggin@gmail.com/","date":"2017-09-07T14:51:44","name":"[RFC,4/8] powerpc/64s/radix: Implement _tlbie(l)_va_range flush functions","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"a40c8749eb08a3c57796046bf0351afa9f11c18a","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/?format=json","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170907145148.24398-5-npiggin@gmail.com/mbox/","series":[{"id":2010,"url":"http://patchwork.ozlabs.org/api/series/2010/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=2010","date":"2017-09-07T14:51:40","name":"Further radix TLB flush optimisations","version":1,"mbox":"http://patchwork.ozlabs.org/series/2010/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811063/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811063/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp3Yt39qZz9s81\n\tfor ;\n\tFri, 8 Sep 2017 01:01:22 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xp3Yt22LMzDrWY\n\tfor ;\n\tFri, 8 Sep 2017 01:01:22 +1000 (AEST)","from mail-pg0-x244.google.com (mail-pg0-x244.google.com\n\t[IPv6:2607:f8b0:400e:c05::244])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xp3Mc5STtzDrXs\n\tfor ;\n\tFri, 8 Sep 2017 00:52:28 +1000 (AEST)","by mail-pg0-x244.google.com with SMTP id m9so5058072pgd.0\n\tfor ;\n\tThu, 07 Sep 2017 07:52:28 -0700 (PDT)","from roar.au.ibm.com (203-219-56-202.tpgi.com.au. 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V\" ,\n\tNicholas Piggin , Anton Blanchard ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"Move the barriers and range iteration down into the _tlbie* level,\nwhich improves readability.\n\nSigned-off-by: Nicholas Piggin \n---\n arch/powerpc/mm/tlb-radix.c | 70 ++++++++++++++++++++++++++-------------------\n 1 file changed, 40 insertions(+), 30 deletions(-)","diff":"diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c\nindex c30f3faf5356..1d3cbc01596d 100644\n--- a/arch/powerpc/mm/tlb-radix.c\n+++ b/arch/powerpc/mm/tlb-radix.c\n@@ -85,7 +85,7 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)\n }\n \n static inline void __tlbiel_va(unsigned long va, unsigned long pid,\n-\t\t\t unsigned long ap, unsigned long ric)\n+\t\t\t unsigned long ap, unsigned long ric)\n {\n \tunsigned long rb,rs,prs,r;\n \n@@ -101,13 +101,28 @@ static inline void __tlbiel_va(unsigned long va, unsigned long pid,\n }\n \n static inline void _tlbiel_va(unsigned long va, unsigned long pid,\n-\t\t\t unsigned long ap, unsigned long ric)\n+\t\t\t unsigned long psize, unsigned long ric)\n {\n+\tunsigned long ap = mmu_get_ap(psize);\n+\n \tasm volatile(\"ptesync\": : :\"memory\");\n \t__tlbiel_va(va, pid, ap, ric);\n \tasm volatile(\"ptesync\": : :\"memory\");\n }\n \n+static inline void _tlbiel_va_range(unsigned long start, unsigned long end,\n+\t\t\t\t unsigned long pid, unsigned long page_size,\n+\t\t\t\t unsigned long psize)\n+{\n+\tunsigned long addr;\n+\tunsigned long ap = mmu_get_ap(psize);\n+\n+\tasm volatile(\"ptesync\": : :\"memory\");\n+\tfor (addr = start; addr < end; addr += page_size)\n+\t\t__tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);\n+\tasm volatile(\"ptesync\": : :\"memory\");\n+}\n+\n static inline void __tlbie_va(unsigned long va, unsigned long pid,\n \t\t\t unsigned long ap, unsigned long ric)\n {\n@@ -125,13 +140,27 @@ static inline void __tlbie_va(unsigned long va, unsigned long pid,\n }\n \n static inline void _tlbie_va(unsigned long va, unsigned long pid,\n-\t\t\t unsigned long ap, unsigned long ric)\n+\t\t\t unsigned long psize, unsigned long ric)\n {\n+\tunsigned long ap = mmu_get_ap(psize);\n+\n \tasm volatile(\"ptesync\": : :\"memory\");\n \t__tlbie_va(va, pid, ap, ric);\n \tasm volatile(\"eieio; tlbsync; ptesync\": : :\"memory\");\n }\n \n+static inline void _tlbie_va_range(unsigned long start, unsigned long end,\n+\t\t\t\t unsigned long pid, unsigned long page_size,\n+\t\t\t\t unsigned long psize)\n+{\n+\tunsigned long addr;\n+\tunsigned long ap = mmu_get_ap(psize);\n+\n+\tasm volatile(\"ptesync\": : :\"memory\");\n+\tfor (addr = start; addr < end; addr += page_size)\n+\t\t__tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);\n+\tasm volatile(\"eieio; tlbsync; ptesync\": : :\"memory\");\n+}\n \n /*\n * Base TLB flushing operations:\n@@ -173,12 +202,11 @@ void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmadd\n \t\t\t\t int psize)\n {\n \tunsigned long pid;\n-\tunsigned long ap = mmu_get_ap(psize);\n \n \tpreempt_disable();\n \tpid = mm ? mm->context.id : 0;\n \tif (pid != MMU_NO_CONTEXT)\n-\t\t_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);\n+\t\t_tlbiel_va(vmaddr, pid, psize, RIC_FLUSH_TLB);\n \tpreempt_enable();\n }\n \n@@ -238,16 +266,15 @@ void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,\n \t\t\t\t int psize)\n {\n \tunsigned long pid;\n-\tunsigned long ap = mmu_get_ap(psize);\n \n \tpid = mm ? mm->context.id : 0;\n \tif (unlikely(pid == MMU_NO_CONTEXT))\n \t\treturn;\n \tpreempt_disable();\n \tif (!mm_is_thread_local(mm))\n-\t\t_tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);\n+\t\t_tlbie_va(vmaddr, pid, psize, RIC_FLUSH_TLB);\n \telse\n-\t\t_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);\n+\t\t_tlbiel_va(vmaddr, pid, psize, RIC_FLUSH_TLB);\n \tpreempt_enable();\n }\n \n@@ -331,9 +358,7 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,\n \t\t\t\t unsigned long end, int psize)\n {\n \tunsigned long pid;\n-\tunsigned long addr;\n \tbool local;\n-\tunsigned long ap = mmu_get_ap(psize);\n \tunsigned long page_size = 1UL << mmu_psize_defs[psize].shift;\n \n \tpid = mm ? mm->context.id : 0;\n@@ -350,18 +375,10 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,\n \t\t\t_tlbie_pid(pid, RIC_FLUSH_TLB);\n \n \t} else {\n-\t\tasm volatile(\"ptesync\": : :\"memory\");\n-\t\tfor (addr = start; addr < end; addr += page_size) {\n-\n-\t\t\tif (local)\n-\t\t\t\t__tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);\n-\t\t\telse\n-\t\t\t\t__tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);\n-\t\t}\n \t\tif (local)\n-\t\t\tasm volatile(\"ptesync\": : :\"memory\");\n+\t\t\t_tlbiel_va_range(start, end, pid, page_size, psize);\n \t\telse\n-\t\t\tasm volatile(\"eieio; tlbsync; ptesync\": : :\"memory\");\n+\t\t\t_tlbie_va_range(start, end, pid, page_size, psize);\n \t}\n \tpreempt_enable();\n }\n@@ -369,7 +386,6 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,\n #ifdef CONFIG_TRANSPARENT_HUGEPAGE\n void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr)\n {\n-\tunsigned long ap = mmu_get_ap(mmu_virtual_psize);\n \tunsigned long pid, end;\n \tbool local;\n \n@@ -392,18 +408,12 @@ void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr)\n \t\t_tlbie_pid(pid, RIC_FLUSH_PWC);\n \n \t/* Then iterate the pages */\n-\tasm volatile(\"ptesync\": : :\"memory\");\n \tend = addr + HPAGE_PMD_SIZE;\n-\tfor (; addr < end; addr += PAGE_SIZE) {\n-\t\tif (local)\n-\t\t\t_tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);\n-\t\telse\n-\t\t\t_tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);\n-\t}\n+\n \tif (local)\n-\t\tasm volatile(\"ptesync\": : :\"memory\");\n+\t\t_tlbiel_va_range(addr, end, pid, PAGE_SIZE, mmu_virtual_psize);\n \telse\n-\t\tasm volatile(\"eieio; tlbsync; ptesync\": : :\"memory\");\n+\t\t_tlbie_va_range(addr, end, pid, PAGE_SIZE, mmu_virtual_psize);\n \tpreempt_enable();\n }\n #endif /* CONFIG_TRANSPARENT_HUGEPAGE */\n","prefixes":["RFC","4/8"]}