{"id":810985,"url":"http://patchwork.ozlabs.org/api/patches/810985/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1504784522-26841-3-git-send-email-yamada.masahiro@socionext.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504784522-26841-3-git-send-email-yamada.masahiro@socionext.com>","list_archive_url":null,"date":"2017-09-07T11:41:58","name":"[v4,2/6] irqdomain: clear trigger type in irq_domain_push_irq()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"cfe7245c998d3f812e9214cc5fe6956e12da20be","submitter":{"id":65882,"url":"http://patchwork.ozlabs.org/api/people/65882/?format=json","name":"Masahiro Yamada","email":"yamada.masahiro@socionext.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1504784522-26841-3-git-send-email-yamada.masahiro@socionext.com/mbox/","series":[{"id":1983,"url":"http://patchwork.ozlabs.org/api/series/1983/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=1983","date":"2017-09-07T11:41:57","name":"irqdomain, gpio: expand irq_domain_push_irq() for DT use and use it for GPIO","version":4,"mbox":"http://patchwork.ozlabs.org/series/1983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810985/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810985/checks/","tags":{},"related":[],"headers":{"Return-Path":"<linux-gpio-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=nifty.com header.i=@nifty.com\n\theader.b=\"hhdWwkFY\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnzDQ1gDVz9s2G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu,  7 Sep 2017 21:45:58 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755288AbdIGLpa (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 7 Sep 2017 07:45:30 -0400","from conuserg-09.nifty.com ([210.131.2.76]:17249 \"EHLO\n\tconuserg-09.nifty.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1755222AbdIGLn7 (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Thu, 7 Sep 2017 07:43:59 -0400","from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp\n\t[153.142.97.92]) (authenticated)\n\tby conuserg-09.nifty.com with ESMTP id v87BgcP0021413;\n\tThu, 7 Sep 2017 20:42:41 +0900"],"DKIM-Filter":"OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v87BgcP0021413","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n\ts=dec2015msa; t=1504784562;\n\tbh=IBfDz1kQGKy4HSf4gyTyv3RWhyF3TqSGq+5ofwdc88c=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=hhdWwkFY2VVgmfK0BafD18nwODXyKoX6Unz5z44F79J+KOq4TZpRNYmtsTFhgr9P7\n\tOddeSwrxCFitHaeJCk+MEOT93qOgBR7wif0IoMZ+ZumYdcaUnRSWJDNE5W2PZNv0sN\n\t8uEf2IWrg6yoiZ/mn0/a81/wKvZac5i8XcNqVV3RxZ92kGtkJ2qgGTRvuSjjzNNZdR\n\tcdosmVRClAqChK2I/DBiZn842Ni9WM4PDOM9GjXy7h/wyG/+zMhYzEAW569+Ijzjmh\n\t3PjVuPHBGwtilYnT3Bh+iALSdMZx5MqvhFtyCffma+REfxNaCChu8KBcFatdH1dxgl\n\t0b8ybjMPLFDHQ==","X-Nifty-SrcIP":"[153.142.97.92]","From":"Masahiro Yamada <yamada.masahiro@socionext.com>","To":"Marc Zyngier <marc.zyngier@arm.com>,\n\tThomas Gleixner <tglx@linutronix.de>,\n\tLinus Walleij <linus.walleij@linaro.org>,\n\tlinux-gpio@vger.kernel.org, Rob Herring <robh+dt@kernel.org>","Cc":"Jassi Brar <jaswinder.singh@linaro.org>,\n\tdevicetree@vger.kernel.org, Jason Cooper <jason@lakedaemon.net>,\n\tMasami Hiramatsu <mhiramat@kernel.org>,\n\tDavid Daney <david.daney@cavium.com>,\n\tMasahiro Yamada <yamada.masahiro@socionext.com>,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH v4 2/6] irqdomain: clear trigger type in\n\tirq_domain_push_irq()","Date":"Thu,  7 Sep 2017 20:41:58 +0900","Message-Id":"<1504784522-26841-3-git-send-email-yamada.masahiro@socionext.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com>","References":"<1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com>","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-gpio.vger.kernel.org>","X-Mailing-List":"linux-gpio@vger.kernel.org"},"content":"Prior to the addition of irq_domain_push_irq(), the hierarchy\nIRQ domain always allocates IRQs from the outer-most domain.\nEach irqchip usually calls irq_domain_alloc_irqs_parent(),\nascending the topology up to the root irqchip.\n\nThe brand-new function irq_domain_push_irq() allows us to allocate\nIRQs for parent domain first, then add a child irq_data to the\ntail of the chain.\n\nFor the new use-case, if the parent sets a temporary trigger type,\nit may differ from the type requested to the outer-most irqchip,\nthen irq_create_fwspec_mapping() warns \"type mismatch, failed to map...\"\n\nClear the trigger type when a new irq_data is connected to the chain.\n\nSigned-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>\n---\n\nChanges in v4:\n  - Newly added\n\n\n kernel/irq/irqdomain.c | 3 +++\n 1 file changed, 3 insertions(+)","diff":"diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c\nindex da3e0b6..18d11b9 100644\n--- a/kernel/irq/irqdomain.c\n+++ b/kernel/irq/irqdomain.c\n@@ -1532,6 +1532,9 @@ int irq_domain_push_irq(struct irq_domain *domain, int virq, void *arg)\n \ttail_irq_data->chip = NULL;\n \ttail_irq_data->chip_data = NULL;\n \n+\t/* clear the trigger type to avoid \"type mismatch\" error */\n+\tirqd_set_trigger_type(tail_irq_data, IRQ_TYPE_NONE);\n+\n \t/* May (probably does) set hwirq, chip, etc. */\n \trv = irq_domain_alloc_irqs_hierarchy(domain, virq, 1, arg);\n \tif (rv) {\n","prefixes":["v4","2/6"]}