{"id":810822,"url":"http://patchwork.ozlabs.org/api/patches/810822/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/patch/1504737309-26981-1-git-send-email-arbab@linux.vnet.ibm.com/","project":{"id":44,"url":"http://patchwork.ozlabs.org/api/projects/44/?format=json","name":"skiboot firmware development","link_name":"skiboot","list_id":"skiboot.lists.ozlabs.org","list_email":"skiboot@lists.ozlabs.org","web_url":"http://github.com/open-power/skiboot","scm_url":"http://github.com/open-power/skiboot","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504737309-26981-1-git-send-email-arbab@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-09-06T22:35:09","name":"npu2: hw-procedures: Enable low power mode","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"73f118727fd8f49ba4c926307915e2bdc1051b71","submitter":{"id":69358,"url":"http://patchwork.ozlabs.org/api/people/69358/?format=json","name":"Reza Arbab","email":"arbab@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/skiboot/patch/1504737309-26981-1-git-send-email-arbab@linux.vnet.ibm.com/mbox/","series":[{"id":1894,"url":"http://patchwork.ozlabs.org/api/series/1894/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/list/?series=1894","date":"2017-09-06T22:35:09","name":"npu2: hw-procedures: Enable low power mode","version":1,"mbox":"http://patchwork.ozlabs.org/series/1894/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810822/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810822/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xndhG6PL3z9s82\n\tfor ;\n\tThu, 7 Sep 2017 08:35:26 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xndhG5fBlzDrWH\n\tfor ;\n\tThu, 7 Sep 2017 08:35:26 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xndh65KGBzDrVj\n\tfor ; Thu, 7 Sep 2017 08:35:17 +1000 (AEST)","from pps.filterd (m0098419.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv86MNuVe090721\n\tfor ; Wed, 6 Sep 2017 18:35:15 -0400","from e18.ny.us.ibm.com (e18.ny.us.ibm.com [129.33.205.208])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2ctq9s2ykg-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Wed, 06 Sep 2017 18:35:14 -0400","from localhost\n\tby e18.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00913269; UDB=6.00458350;\n\tIPR=6.00693531; \n\tBA=6.00005574; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017041;\n\tXFM=3.00000015; UTC=2017-09-06 22:35:12","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17090622-0045-0000-0000-000007B91D7C","Message-Id":"<1504737309-26981-1-git-send-email-arbab@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-06_07:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709060319","Subject":"[Skiboot] [PATCH] npu2: hw-procedures: Enable low power mode","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Popple ,\n\tAndrew Donnellan ","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"},"content":"Add a procedure which sets the NTL low power config register.\n\nSigned-off-by: Reza Arbab \n---\n hw/npu2-hw-procedures.c | 18 +++++++++++++++++-\n include/npu2-regs.h | 6 ++++++\n 2 files changed, 23 insertions(+), 1 deletion(-)","diff":"diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c\nindex a140aed..24feb03 100644\n--- a/hw/npu2-hw-procedures.c\n+++ b/hw/npu2-hw-procedures.c\n@@ -310,9 +310,25 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev)\n \t\tphy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);\n \t}\n \n+\treturn PROCEDURE_NEXT;\n+}\n+\n+/* Procedure 1.2.11 - Enable Low Power Mode */\n+static uint32_t enable_low_power(struct npu2_dev *ndev)\n+{\n+\tuint64_t val;\n+\n+\tval = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE, 0ull, 1);\n+\tval = SETFIELD(NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG, val, 1);\n+\tval = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH, val, 8);\n+\tval = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH, val, 15);\n+\tval = SETFIELD(NPU2_NTL_LOW_POWER_CFG_CNT_THRESH, val, 8);\n+\tnpu2_write(ndev->npu, NPU2_NTL_LOW_POWER_CFG(ndev), val);\n+\n \treturn PROCEDURE_COMPLETE;\n }\n-DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete);\n+DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete,\n+\t\t enable_low_power);\n \n /* Procedure 1.2.6 - I/O PHY Tx Impedance Calibration */\n static uint32_t phy_tx_zcal(struct npu2_dev *ndev)\ndiff --git a/include/npu2-regs.h b/include/npu2-regs.h\nindex 86e2658..24d8549 100644\n--- a/include/npu2-regs.h\n+++ b/include/npu2-regs.h\n@@ -248,6 +248,12 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);\n #define NPU2_NTL_MISC_CFG1(ndev)\t\tNPU2_NTLU_REG_OFFSET(ndev, 0x0C0)\n #define NPU2_NTL_SCRATCH1(ndev)\t\t\tNPU2_NTLU_REG_OFFSET(ndev, 0x0D0)\n #define NPU2_NTL_LOW_POWER_CFG(ndev)\t\tNPU2_NTLU_REG_OFFSET(ndev, 0x0E0)\n+#define NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE\t\tPPC_BIT(0)\n+#define NPU2_NTL_LOW_POWER_CFG_ONLY_MODE\t\tPPC_BIT(1)\n+#define NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG\tPPC_BITMASK(2,7)\n+#define NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH\tPPC_BITMASK(8,19)\n+#define NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH\tPPC_BITMASK(20,31)\n+#define NPU2_NTL_LOW_POWER_CFG_CNT_THRESH\t\tPPC_BITMASK(32,43)\n #define NPU2_NTL_DBG_INHIBIT_CFG(ndev)\t\tNPU2_NTL_REG_OFFSET(ndev, 0x220)\n #define NPU2_NTL_DISPLAY_CTL(ndev)\t\tNPU2_NTL_REG_OFFSET(ndev, 0x280)\n #define NPU2_NTL_DISPLAY_DATA0(ndev)\t\tNPU2_NTL_REG_OFFSET(ndev, 0x288)\n","prefixes":[]}