{"id":810785,"url":"http://patchwork.ozlabs.org/api/patches/810785/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170906203839.GB8065@us.ibm.com/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<20170906203839.GB8065@us.ibm.com>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/20170906203839.GB8065@us.ibm.com/","date":"2017-09-06T20:38:39","name":"[RFC,v3,1/1] powerpc: Add support for setting SPRN_TIDR","commit_ref":null,"pull_url":null,"state":"rfc","archived":false,"hash":"f55cc71621cdeae4e3899fbc27f58f8378571d8c","submitter":{"id":984,"url":"http://patchwork.ozlabs.org/api/people/984/?format=json","name":"Sukadev Bhattiprolu","email":"sukadev@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170906203839.GB8065@us.ibm.com/mbox/","series":[{"id":1875,"url":"http://patchwork.ozlabs.org/api/series/1875/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=1875","date":"2017-09-06T20:38:39","name":"[RFC,v3,1/1] powerpc: Add support for setting SPRN_TIDR","version":3,"mbox":"http://patchwork.ozlabs.org/series/1875/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810785/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810785/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnb742n73z9ryQ\n\tfor ;\n\tThu, 7 Sep 2017 06:40:00 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xnb741r7hzDrWp\n\tfor ;\n\tThu, 7 Sep 2017 06:40:00 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xnb5j68dgzDrKk\n\tfor ;\n\tThu, 7 Sep 2017 06:38:49 +1000 (AEST)","from pps.filterd (m0098393.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv86KVTAj138315\n\tfor ; Wed, 6 Sep 2017 16:38:47 -0400","from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2ctmy2gphp-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Wed, 06 Sep 2017 16:38:47 -0400","from localhost\n\tby e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tWed, 6 Sep 2017 16:38:41 -0400","from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com\n\t[9.57.199.111])\n\tby b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid v86Kcfsq31588448; Wed, 6 Sep 2017 20:38:41 GMT","from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 6044DAC03A;\n\tWed, 6 Sep 2017 16:39:08 -0400 (EDT)","from suka-w540.localdomain (unknown [9.70.94.25])\n\tby b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP id 17165AC03F;\n\tWed, 6 Sep 2017 16:39:08 -0400 (EDT)","by suka-w540.localdomain (Postfix, from userid 1000)\n\tid 6BBAB228F9A; Wed, 6 Sep 2017 13:38:39 -0700 (PDT)"],"Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=sukadev@linux.vnet.ibm.com; receiver=)","Date":"Wed, 6 Sep 2017 13:38:39 -0700","From":"Sukadev Bhattiprolu ","To":"benh@us.ibm.com, Michael Ellerman , mikey@neuling.org","Subject":"[RFC PATCH v3 1/1] powerpc: Add support for setting SPRN_TIDR","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","X-Operating-System":"Linux 2.0.32 on an i486","User-Agent":"Mutt/1.7.1 (2016-10-04)","X-TM-AS-GCONF":"00","x-cbid":"17090620-0024-0000-0000-000002CD132A","X-IBM-SpamModules-Scores":"","X-IBM-SpamModules-Versions":"BY=3.00007679; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00913230; UDB=6.00458328;\n\tIPR=6.00693493; \n\tBA=6.00005574; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017039;\n\tXFM=3.00000015; UTC=2017-09-06 20:38:43","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17090620-0025-0000-0000-0000455756BB","Message-Id":"<20170906203839.GB8065@us.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-06_06:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=2\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709060294","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"felix@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org,\n\tclombard@linux.vnet.ibm.com, linux-kernel@vger.kernel.org","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"We need the SPRN_TIDR to be set for use with fast thread-wakeup (core-\nto-core wakeup) and also with CAPI.\n\nEach thread in a process needs to have a unique id within the process.\nBut as explained below, for now, we assign globally unique thread ids\nto all threads in the system.\n\nSigned-off-by: Sukadev Bhattiprolu \nSigned-off-by: Philippe Bergheaud \nSigned-off-by: Christophe Lombard \n---\nChangelog[v3]\n\t- Merge changes with and address comments to Christophe's patch.\n\t (i.e drop CONFIG_PPC_VAS; use CONFIG_PPC64; check CPU_ARCH_300\n\t before setting TIDR). Defer following to separate patches:\n\t \t- emulation parts of Christophe's patch,\n\t\t- setting TIDR for tasks other than 'current'\n\t\t- setting feature bit in AT_HWCAP2\n\nChangelog[v2]\n\t- Michael Ellerman: Use an interface to assign TIDR so it is\n\t assigned to only threads that need it; move assignment to\n\t restore_sprs(). Drop lint from rebase;\n---\n arch/powerpc/include/asm/processor.h | 1 +\n arch/powerpc/include/asm/switch_to.h | 3 +\n arch/powerpc/kernel/process.c | 120 +++++++++++++++++++++++++++++++++++\n 3 files changed, 124 insertions(+)","diff":"diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h\nindex fab7ff8..58cc212 100644\n--- a/arch/powerpc/include/asm/processor.h\n+++ b/arch/powerpc/include/asm/processor.h\n@@ -329,6 +329,7 @@ struct thread_struct {\n \t */\n \tint\t\tdscr_inherit;\n \tunsigned long\tppr;\t/* used to save/restore SMT priority */\n+\tunsigned long\ttidr;\n #endif\n #ifdef CONFIG_PPC_BOOK3S_64\n \tunsigned long\ttar;\ndiff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h\nindex 17c8380..f5da32f 100644\n--- a/arch/powerpc/include/asm/switch_to.h\n+++ b/arch/powerpc/include/asm/switch_to.h\n@@ -91,4 +91,7 @@ static inline void clear_task_ebb(struct task_struct *t)\n #endif\n }\n \n+extern int set_thread_tidr(struct task_struct *t);\n+extern void clear_thread_tidr(struct task_struct *t);\n+\n #endif /* _ASM_POWERPC_SWITCH_TO_H */\ndiff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c\nindex a0c74bb..8e992e9 100644\n--- a/arch/powerpc/kernel/process.c\n+++ b/arch/powerpc/kernel/process.c\n@@ -1120,6 +1120,13 @@ static inline void restore_sprs(struct thread_struct *old_thread,\n \t\t\tmtspr(SPRN_TAR, new_thread->tar);\n \t}\n #endif\n+#ifdef CONFIG_PPC64\n+\tif (old_thread->tidr != new_thread->tidr) {\n+\t\t/* TIDR should be non-zero only with ISA3.0. */\n+\t\tWARN_ON_ONCE(!cpu_has_feature(CPU_FTR_ARCH_300));\n+\t\tmtspr(SPRN_TIDR, new_thread->tidr);\n+\t}\n+#endif\n }\n \n #ifdef CONFIG_PPC_BOOK3S_64\n@@ -1434,9 +1441,117 @@ void flush_thread(void)\n #endif /* CONFIG_HAVE_HW_BREAKPOINT */\n }\n \n+#ifdef CONFIG_PPC64\n+static DEFINE_SPINLOCK(vas_thread_id_lock);\n+static DEFINE_IDA(vas_thread_ida);\n+\n+/*\n+ * We need to assign a unique thread id to each thread in a process.\n+ *\n+ * This thread id, referred to as TIDR, and separate from the Linux's tgid,\n+ * is intended to be used to direct an ASB_Notify from the hardware to the\n+ * thread, when a suitable event occurs in the system.\n+ *\n+ * One such event is a \"paste\" instruction in the context of Fast Thread\n+ * Wakeup (aka Core-to-core wake up in the Virtual Accelerator Switchboard\n+ * (VAS) in POWER9.\n+ *\n+ * To get a unique TIDR per process we could simply reuse task_pid_nr() but\n+ * the problem is that task_pid_nr() is not yet available copy_thread() is\n+ * called. Fixing that would require changing more intrusive arch-neutral\n+ * code in code path in copy_process()?.\n+ *\n+ * Further, to assign unique TIDRs within each process, we need an atomic\n+ * field (or an IDR) in task_struct, which again intrudes into the arch-\n+ * neutral code. So try to assign globally unique TIDRs for now.\n+ *\n+ * NOTE: TIDR 0 indicates that the thread does not need a TIDR value.\n+ * \t For now, only threads that expect to be notified by the VAS\n+ * \t hardware need a TIDR value and we assign values > 0 for those.\n+ */\n+#define MAX_THREAD_CONTEXT\t((1 << 16) - 1)\n+static int assign_thread_tidr(void)\n+{\n+\tint index;\n+\tint err;\n+\n+again:\n+\tif (!ida_pre_get(&vas_thread_ida, GFP_KERNEL))\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock(&vas_thread_id_lock);\n+\terr = ida_get_new_above(&vas_thread_ida, 1, &index);\n+\tspin_unlock(&vas_thread_id_lock);\n+\n+\tif (err == -EAGAIN)\n+\t\tgoto again;\n+\telse if (err)\n+\t\treturn err;\n+\n+\tif (index > MAX_THREAD_CONTEXT) {\n+\t\tspin_lock(&vas_thread_id_lock);\n+\t\tida_remove(&vas_thread_ida, index);\n+\t\tspin_unlock(&vas_thread_id_lock);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn index;\n+}\n+\n+static void free_thread_tidr(int id)\n+{\n+\tspin_lock(&vas_thread_id_lock);\n+\tida_remove(&vas_thread_ida, id);\n+\tspin_unlock(&vas_thread_id_lock);\n+}\n+\n+/*\n+ * Clear any TIDR value assigned to this thread.\n+ */\n+void clear_thread_tidr(struct task_struct *t)\n+{\n+\tif (!t->thread.tidr)\n+\t\treturn;\n+\n+\tif (!cpu_has_feature(CPU_FTR_ARCH_300)) {\n+\t\tWARN_ON_ONCE(1);\n+\t\treturn;\n+\t}\n+\n+\tmtspr(SPRN_TIDR, 0);\n+\tfree_thread_tidr(t->thread.tidr);\n+\tt->thread.tidr = 0;\n+}\n+\n+/*\n+ * Assign a unique TIDR (thread id) for task @t and set it in the thread\n+ * structure. For now, we only support setting TIDR for 'current' task.\n+ */\n+int set_thread_tidr(struct task_struct *t)\n+{\n+\tif (!cpu_has_feature(CPU_FTR_ARCH_300))\n+\t\treturn -EINVAL;\n+\n+\tif (t != current)\n+\t\treturn -EINVAL;\n+\n+\tt->thread.tidr = assign_thread_tidr();\n+\tif (t->thread.tidr < 0)\n+\t\treturn t->thread.tidr;\n+\n+\tmtspr(SPRN_TIDR, t->thread.tidr);\n+\n+\treturn 0;\n+}\n+\n+#endif /* CONFIG_PPC64 */\n+\n void\n release_thread(struct task_struct *t)\n {\n+#ifdef CONFIG_PPC64\n+\tclear_thread_tidr(t);\n+#endif\n }\n \n /*\n@@ -1462,6 +1577,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)\n \n \tclear_task_ebb(dst);\n \n+\tdst->thread.tidr = 0;\n+\n \treturn 0;\n }\n \n@@ -1572,6 +1689,9 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,\n #endif\n \n \tsetup_ksp_vsid(p, sp);\n+#ifdef CONFIG_PPC64\n+\tp->thread.tidr = 0;\n+#endif\n \n #ifdef CONFIG_PPC64 \n \tif (cpu_has_feature(CPU_FTR_DSCR)) {\n","prefixes":["RFC","v3","1/1"]}