{"id":810755,"url":"http://patchwork.ozlabs.org/api/patches/810755/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150472219643.24907.18130899263866950639.stgit@frigg.lan/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<150472219643.24907.18130899263866950639.stgit@frigg.lan>","list_archive_url":null,"date":"2017-09-06T18:23:16","name":"[v4,15/20] trace: Introduce a proper structure to describe memory accesses","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6f7d134a61b9a030a672afb3be60577b0c27e496","submitter":{"id":9099,"url":"http://patchwork.ozlabs.org/api/people/9099/?format=json","name":"Lluís Vilanova","email":"vilanova@ac.upc.edu"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150472219643.24907.18130899263866950639.stgit@frigg.lan/mbox/","series":[{"id":1859,"url":"http://patchwork.ozlabs.org/api/series/1859/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1859","date":"2017-09-06T17:22:41","name":"instrument: Add basic event instrumentation","version":4,"mbox":"http://patchwork.ozlabs.org/series/1859/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810755/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810755/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnX664GNDz9sRY\n\tfor ;\n\tThu, 7 Sep 2017 04:23:58 +1000 (AEST)","from localhost ([::1]:37422 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpezU-0006JF-Kh\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 14:23:56 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:51709)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpezA-0006Ix-6k\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 14:23:38 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dpez4-000806-ST\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 14:23:36 -0400","from roura.ac.upc.es ([147.83.33.10]:50999)\n\tby eggs.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpez4-0007zk-D6\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 14:23:30 -0400","from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91])\n\tby roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v86INNiT005145;\n\tWed, 6 Sep 2017 20:23:23 +0200","from localhost (unknown [31.210.187.58])\n\tby correu-1.ac.upc.es (Postfix) with ESMTPSA id DC520355;\n\tWed, 6 Sep 2017 20:23:17 +0200 (CEST)"],"From":"=?utf-8?b?TGx1w61z?= Vilanova ","To":"qemu-devel@nongnu.org","Date":"Wed, 6 Sep 2017 21:23:16 +0300","Message-Id":"<150472219643.24907.18130899263866950639.stgit@frigg.lan>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<150471856141.24907.274176769201097378.stgit@frigg.lan>","References":"<150471856141.24907.274176769201097378.stgit@frigg.lan>","User-Agent":"StGit/0.17.1-dirty","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","X-MIME-Autoconverted":"from 8bit to quoted-printable by roura.ac.upc.es id\n\tv86INNiT005145","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy]","X-Received-From":"147.83.33.10","Subject":"[Qemu-devel] [PATCH v4 15/20] trace: Introduce a proper structure\n\tto describe memory accesses","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Crosthwaite ,\n\t\"Emilio G. Cota\" ,\n\tStefan Hajnoczi , \n\tPaolo Bonzini , Richard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Signed-off-by: Lluís Vilanova \n---\n include/exec/cpu_ldst_template.h | 15 ++++++--------\n include/exec/cpu_ldst_useronly_template.h | 15 ++++++--------\n tcg/tcg-op.c | 22 +++++++++++++--------\n trace/mem-internal.h | 22 ++++++++++++---------\n trace/mem.h | 31 +++++++++++++++++++++++++----\n 5 files changed, 66 insertions(+), 39 deletions(-)","diff":"diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h\nindex 4db2302962..debbabcfb2 100644\n--- a/include/exec/cpu_ldst_template.h\n+++ b/include/exec/cpu_ldst_template.h\n@@ -88,9 +88,8 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,\n TCGMemOpIdx oi;\n \n #if !defined(SOFTMMU_CODE_ACCESS)\n- trace_guest_mem_before_exec(\n- ENV_GET_CPU(env), ptr,\n- trace_mem_build_info(SHIFT, false, MO_TE, false));\n+ TraceMemInfo meminfo = trace_mem_build_info(SHIFT, false, MO_TE, false);\n+ trace_guest_mem_before_exec(ENV_GET_CPU(env), ptr, meminfo.raw);\n #endif\n \n addr = ptr;\n@@ -126,9 +125,8 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,\n TCGMemOpIdx oi;\n \n #if !defined(SOFTMMU_CODE_ACCESS)\n- trace_guest_mem_before_exec(\n- ENV_GET_CPU(env), ptr,\n- trace_mem_build_info(SHIFT, true, MO_TE, false));\n+ TraceMemInfo meminfo = trace_mem_build_info(SHIFT, true, MO_TE, false);\n+ trace_guest_mem_before_exec(ENV_GET_CPU(env), ptr, meminfo.raw);\n #endif\n \n addr = ptr;\n@@ -168,9 +166,8 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,\n TCGMemOpIdx oi;\n \n #if !defined(SOFTMMU_CODE_ACCESS)\n- trace_guest_mem_before_exec(\n- ENV_GET_CPU(env), ptr,\n- trace_mem_build_info(SHIFT, false, MO_TE, true));\n+ TraceMemInfo meminfo = trace_mem_build_info(SHIFT, false, MO_TE, true);\n+ trace_guest_mem_before_exec(ENV_GET_CPU(env), ptr, meminfo.raw);\n #endif\n \n addr = ptr;\ndiff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h\nindex 7b8c7c506e..b0b3fc1b8d 100644\n--- a/include/exec/cpu_ldst_useronly_template.h\n+++ b/include/exec/cpu_ldst_useronly_template.h\n@@ -61,9 +61,8 @@ static inline RES_TYPE\n glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)\n {\n #if !defined(CODE_ACCESS)\n- trace_guest_mem_before_exec(\n- ENV_GET_CPU(env), ptr,\n- trace_mem_build_info(DATA_SIZE, false, MO_TE, false));\n+ TraceMemInfo meminfo = trace_mem_build_info(DATA_SIZE, false, MO_TE, false);\n+ trace_guest_mem_before_exec(ENV_GET_CPU(env), ptr, meminfo.raw);\n #endif\n return glue(glue(ld, USUFFIX), _p)(g2h(ptr));\n }\n@@ -81,9 +80,8 @@ static inline int\n glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)\n {\n #if !defined(CODE_ACCESS)\n- trace_guest_mem_before_exec(\n- ENV_GET_CPU(env), ptr,\n- trace_mem_build_info(DATA_SIZE, true, MO_TE, false));\n+ TraceMemInfo meminfo = trace_mem_build_info(DATA_SIZE, true, MO_TE, false);\n+ trace_guest_mem_before_exec(ENV_GET_CPU(env), ptr, meminfo.raw);\n #endif\n return glue(glue(lds, SUFFIX), _p)(g2h(ptr));\n }\n@@ -103,9 +101,8 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,\n RES_TYPE v)\n {\n #if !defined(CODE_ACCESS)\n- trace_guest_mem_before_exec(\n- ENV_GET_CPU(env), ptr,\n- trace_mem_build_info(DATA_SIZE, false, MO_TE, true));\n+ TraceMemInfo meminfo = trace_mem_build_info(DATA_SIZE, false, MO_TE, true);\n+ trace_guest_mem_before_exec(ENV_GET_CPU(env), ptr, meminfo.raw);\n #endif\n glue(glue(st, SUFFIX), _p)(g2h(ptr), v);\n }\ndiff --git a/tcg/tcg-op.c b/tcg/tcg-op.c\nindex 87f673ef49..234e300ede 100644\n--- a/tcg/tcg-op.c\n+++ b/tcg/tcg-op.c\n@@ -2664,22 +2664,26 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,\n \n void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ TraceMemInfo meminfo;\n memop = tcg_canonicalize_memop(memop, 0, 0);\n- trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n- addr, trace_mem_get_info(memop, 0));\n+ meminfo = trace_mem_get_info(memop, 0);\n+ trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo.raw);\n gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx);\n }\n \n void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ TraceMemInfo meminfo;\n memop = tcg_canonicalize_memop(memop, 0, 1);\n- trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n- addr, trace_mem_get_info(memop, 1));\n+ meminfo = trace_mem_get_info(memop, 1);\n+ trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo.raw);\n gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx);\n }\n \n void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ TraceMemInfo meminfo;\n+\n if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {\n tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);\n if (memop & MO_SIGN) {\n@@ -2691,21 +2695,23 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n }\n \n memop = tcg_canonicalize_memop(memop, 1, 0);\n- trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n- addr, trace_mem_get_info(memop, 0));\n+ meminfo = trace_mem_get_info(memop, 0);\n+ trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo.raw);\n gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx);\n }\n \n void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ TraceMemInfo meminfo;\n+\n if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {\n tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);\n return;\n }\n \n memop = tcg_canonicalize_memop(memop, 1, 1);\n- trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n- addr, trace_mem_get_info(memop, 1));\n+ meminfo = trace_mem_get_info(memop, 1);\n+ trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo.raw);\n gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx);\n }\n \ndiff --git a/trace/mem-internal.h b/trace/mem-internal.h\nindex ddda934253..b77079527f 100644\n--- a/trace/mem-internal.h\n+++ b/trace/mem-internal.h\n@@ -1,7 +1,7 @@\n /*\n * Helper functions for guest memory tracing\n *\n- * Copyright (C) 2016 Lluís Vilanova \n+ * Copyright (C) 2016-2017 Lluís Vilanova \n *\n * This work is licensed under the terms of the GNU GPL, version 2 or later.\n * See the COPYING file in the top-level directory.\n@@ -10,8 +10,9 @@\n #ifndef TRACE__MEM_INTERNAL_H\n #define TRACE__MEM_INTERNAL_H\n \n-static inline uint8_t trace_mem_get_info(TCGMemOp op, bool store)\n+static inline TraceMemInfo trace_mem_get_info(TCGMemOp op, bool store)\n {\n+ TraceMemInfo res_;\n uint8_t res = op;\n bool be = (op & MO_BSWAP) == MO_BE;\n \n@@ -27,19 +28,22 @@ static inline uint8_t trace_mem_get_info(TCGMemOp op, bool store)\n res |= 1ULL << 4;\n }\n \n- return res;\n+ res_.raw = res;\n+ return res_;\n }\n \n-static inline uint8_t trace_mem_build_info(\n+static inline TraceMemInfo trace_mem_build_info(\n TCGMemOp size, bool sign_extend, TCGMemOp endianness, bool store)\n {\n- uint8_t res = 0;\n- res |= size;\n- res |= (sign_extend << 2);\n+ TraceMemInfo res;\n+ res.size_shift = size;\n+ res.sign_extend = sign_extend;\n if (endianness == MO_BE) {\n- res |= (1ULL << 3);\n+ res.endianness = 1;\n+ } else {\n+ res.endianness = 0;\n }\n- res |= (store << 4);\n+ res.store = store;\n return res;\n }\n \ndiff --git a/trace/mem.h b/trace/mem.h\nindex 9c88bcb4e6..9866b41401 100644\n--- a/trace/mem.h\n+++ b/trace/mem.h\n@@ -1,7 +1,7 @@\n /*\n * Helper functions for guest memory tracing\n *\n- * Copyright (C) 2016 Lluís Vilanova \n+ * Copyright (C) 2016-2017 Lluís Vilanova \n *\n * This work is licensed under the terms of the GNU GPL, version 2 or later.\n * See the COPYING file in the top-level directory.\n@@ -12,21 +12,44 @@\n \n #include \"tcg/tcg.h\"\n \n+/**\n+ * TraceMemInfo:\n+ * @size_shift: Memoy access size, interpreted as \"1 << size_shift\" bytes.\n+ * @sign_extend: Whether the access is sign-extended.\n+ * @endianness: Endinness type (0: little, 1: big).\n+ * @store: Whether it's a store operation.\n+ *\n+ * Memory access information.\n+ *\n+ * NOTE: Keep in sync with QIMemInfo.\n+ */\n+typedef struct TraceMemInfo {\n+ union {\n+ struct {\n+ uint8_t size_shift : 2;\n+ bool sign_extend: 1;\n+ uint8_t endianness : 1;\n+ bool store : 1;\n+ };\n+ uint8_t raw;\n+ };\n+} TraceMemInfo;\n+\n \n /**\n * trace_mem_get_info:\n *\n * Return a value for the 'info' argument in guest memory access traces.\n */\n-static uint8_t trace_mem_get_info(TCGMemOp op, bool store);\n+static TraceMemInfo trace_mem_get_info(TCGMemOp op, bool store);\n \n /**\n * trace_mem_build_info:\n *\n * Return a value for the 'info' argument in guest memory access traces.\n */\n-static uint8_t trace_mem_build_info(TCGMemOp size, bool sign_extend,\n- TCGMemOp endianness, bool store);\n+static TraceMemInfo trace_mem_build_info(TCGMemOp size, bool sign_extend,\n+ TCGMemOp endianness, bool store);\n \n \n #include \"trace/mem-internal.h\"\n","prefixes":["v4","15/20"]}