{"id":810731,"url":"http://patchwork.ozlabs.org/api/patches/810731/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1504717175-11844-1-git-send-email-suneelglinux@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504717175-11844-1-git-send-email-suneelglinux@gmail.com>","list_archive_url":null,"date":"2017-09-06T16:59:35","name":"[U-Boot,v1] drivers: ahci: write upper 32 bits for clb and fis registers","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"e06692d138646b7062718a45dd4c8abf6c316ea8","submitter":{"id":72058,"url":"http://patchwork.ozlabs.org/api/people/72058/?format=json","name":"Suneel Garapati","email":"suneelglinux@gmail.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1504717175-11844-1-git-send-email-suneelglinux@gmail.com/mbox/","series":[{"id":1856,"url":"http://patchwork.ozlabs.org/api/series/1856/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=1856","date":"2017-09-06T16:59:35","name":"[U-Boot,v1] drivers: ahci: write upper 32 bits for clb and fis registers","version":1,"mbox":"http://patchwork.ozlabs.org/series/1856/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810731/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810731/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"If 64-bit capability is supported, commandlistbase and fis base\nshould be split as lower32 and upper32. upper32 should be\nwritten to PORT_(LST/FIS)_ADDR_HI.\n\nSigned-off-by: Suneel Garapati \n---\n\nChanges v1:\n - add macro definitions for LOWER32, UPPER32\n\n\n drivers/ata/ahci.c | 14 ++++++++++++--\n include/ahci.h | 1 +\n 2 files changed, 13 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c\nindex 5e4df19..178d9a7 100644\n--- a/drivers/ata/ahci.c\n+++ b/drivers/ata/ahci.c\n@@ -27,6 +27,9 @@\n #include \n #include \n \n+#define LOWER32(val)\t(u32)((u64)(val) & 0xFFFFFFFF)\n+#define UPPER32(val)\t(u32)(((u64)(val) & 0xFFFFFFFF00000000ULL) >> 32)\n+\n static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);\n \n #ifndef CONFIG_DM_SCSI\n@@ -607,10 +610,17 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)\n \tpp->cmd_tbl_sg =\n \t\t\t(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);\n \n-\twritel_with_flush((unsigned long)pp->cmd_slot,\n+\tif (uc_priv->cap & HOST_CAP_64)\n+\t\twritel_with_flush(cpu_to_le32(UPPER32(pp->cmd_slot)),\n+\t\t\t\t port_mmio + PORT_LST_ADDR_HI);\n+\twritel_with_flush(cpu_to_le32(LOWER32(pp->cmd_slot)),\n \t\t\t port_mmio + PORT_LST_ADDR);\n \n-\twritel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);\n+\tif (uc_priv->cap & HOST_CAP_64)\n+\t\twritel_with_flush(cpu_to_le32(UPPER32(pp->rx_fis)),\n+\t\t\t\t port_mmio + PORT_FIS_ADDR_HI);\n+\twritel_with_flush(cpu_to_le32(LOWER32(pp->rx_fis)),\n+\t\t\t port_mmio + PORT_FIS_ADDR);\n \n #ifdef CONFIG_SUNXI_AHCI\n \tsunxi_dma_init(port_mmio);\ndiff --git a/include/ahci.h b/include/ahci.h\nindex 33171b7..80e7f13 100644\n--- a/include/ahci.h\n+++ b/include/ahci.h\n@@ -40,6 +40,7 @@\n #define HOST_RESET\t\t(1 << 0) /* reset controller; self-clear */\n #define HOST_IRQ_EN\t\t(1 << 1) /* global IRQ enable */\n #define HOST_AHCI_EN\t\t(1 << 31) /* AHCI enabled */\n+#define HOST_CAP_64\t\t(1 << 31) /* 64bit addressing capability */\n \n /* Registers for each SATA port */\n #define PORT_LST_ADDR\t\t0x00 /* command list DMA addr */\n","prefixes":["U-Boot","v1"]}