{"id":810714,"url":"http://patchwork.ozlabs.org/api/patches/810714/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-24-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-24-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:06:03","name":"[PULL,23/32] target/arm: [tcg, a64] Port to translate_insn","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1d8b2d728628f508884929bf819a2bd974eb44f4","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-24-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810714/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810714/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::22a","Subject":"[Qemu-devel] [PULL 23/32] target/arm: [tcg,\n\ta64] Port to translate_insn","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t, \tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Lluís Vilanova \n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nReviewed-by: Emilio G. Cota \nSigned-off-by: Lluís Vilanova \nMessage-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan>\n[rth: Adjust for translate_insn interface change.]\nSigned-off-by: Richard Henderson \n---\n target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++------------------\n 1 file changed, 43 insertions(+), 28 deletions(-)","diff":"diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex e94198280d..f959f4469a 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -11254,6 +11254,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n dc->is_ldex = false;\n dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);\n \n+ dc->next_page_start =\n+ (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n+\n init_tmp_a64_array(dc);\n \n return max_insns;\n@@ -11291,12 +11294,43 @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n return true;\n }\n \n+static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ CPUARMState *env = cpu->env_ptr;\n+\n+ if (dc->ss_active && !dc->pstate_ss) {\n+ /* Singlestep state is Active-pending.\n+ * If we're in this state at the start of a TB then either\n+ * a) we just took an exception to an EL which is being debugged\n+ * and this is the first insn in the exception handler\n+ * b) debug exceptions were masked and we just unmasked them\n+ * without changing EL (eg by clearing PSTATE.D)\n+ * In either case we're going to take a swstep exception in the\n+ * \"did not step an insn\" case, and so the syndrome ISV and EX\n+ * bits should be zero.\n+ */\n+ assert(dc->base.num_insns == 1);\n+ gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n+ default_exception_el(dc));\n+ dc->base.is_jmp = DISAS_NORETURN;\n+ } else {\n+ disas_a64_insn(env, dc);\n+ }\n+\n+ if (dc->base.is_jmp == DISAS_NEXT) {\n+ if (dc->ss_active || dc->pc >= dc->next_page_start) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n+ }\n+\n+ dc->base.pc_next = dc->pc;\n+}\n+\n void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n TranslationBlock *tb)\n {\n- CPUARMState *env = cs->env_ptr;\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n- target_ulong next_page_start;\n int max_insns;\n \n dc->base.tb = tb;\n@@ -11306,7 +11340,6 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n dc->base.num_insns = 0;\n dc->base.singlestep_enabled = cs->singlestep_enabled;\n \n- next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n max_insns = dc->base.tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n max_insns = CF_COUNT_MASK;\n@@ -11342,42 +11375,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n gen_io_start();\n }\n \n- if (dc->ss_active && !dc->pstate_ss) {\n- /* Singlestep state is Active-pending.\n- * If we're in this state at the start of a TB then either\n- * a) we just took an exception to an EL which is being debugged\n- * and this is the first insn in the exception handler\n- * b) debug exceptions were masked and we just unmasked them\n- * without changing EL (eg by clearing PSTATE.D)\n- * In either case we're going to take a swstep exception in the\n- * \"did not step an insn\" case, and so the syndrome ISV and EX\n- * bits should be zero.\n- */\n- assert(dc->base.num_insns == 1);\n- gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n- default_exception_el(dc));\n- dc->base.is_jmp = DISAS_NORETURN;\n- break;\n- }\n-\n- disas_a64_insn(env, dc);\n+ aarch64_tr_translate_insn(&dc->base, cs);\n \n if (tcg_check_temp_count()) {\n fprintf(stderr, \"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n dc->pc);\n }\n \n+ if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabled ||\n+ singlestep || dc->base.num_insns >= max_insns)) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n+\n /* Translation stops when a conditional branch is encountered.\n * Otherwise the subsequent code could get translated several times.\n * Also stop translation when a page boundary is reached. This\n * ensures prefetch aborts occur at the right place.\n */\n- } while (!dc->base.is_jmp && !tcg_op_buf_full() &&\n- !cs->singlestep_enabled &&\n- !singlestep &&\n- !dc->ss_active &&\n- dc->pc < next_page_start &&\n- dc->base.num_insns < max_insns);\n+ } while (!dc->base.is_jmp);\n \n if (dc->base.tb->cflags & CF_LAST_IO) {\n gen_io_end();\n","prefixes":["PULL","23/32"]}