{"id":810713,"url":"http://patchwork.ozlabs.org/api/patches/810713/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-18-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-18-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:05:57","name":"[PULL,17/32] target/arm: [tcg, a64] Port to init_disas_context","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"38f93e4e31e1d7b088a03eb9dea6808f97cd78b0","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-18-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810713/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810713/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::230","Subject":"[Qemu-devel] [PULL 17/32] target/arm: [tcg,\n\ta64] Port to init_disas_context","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t, \tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Lluís Vilanova \n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova \nReviewed-by: Richard Henderson \nReviewed-by: Alex Benneé \nMessage-Id: <150002340430.22386.10889954302345646107.stgit@frigg.lan>\n[rth: Adjust for max_insns interface change.]\nSigned-off-by: Richard Henderson \n---\n target/arm/translate-a64.c | 38 ++++++++++++++++++++++++--------------\n 1 file changed, 24 insertions(+), 14 deletions(-)","diff":"diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex f5c678ef25..e8dc96c28a 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -11200,21 +11200,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)\n free_tmp_a64(s);\n }\n \n-void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n- TranslationBlock *tb)\n+static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n+ CPUState *cpu, int max_insns)\n {\n- CPUARMState *env = cs->env_ptr;\n- ARMCPU *cpu = arm_env_get_cpu(env);\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n- target_ulong next_page_start;\n- int max_insns;\n-\n- dc->base.tb = tb;\n- dc->base.pc_first = dc->base.tb->pc;\n- dc->base.pc_next = dc->base.pc_first;\n- dc->base.is_jmp = DISAS_NEXT;\n- dc->base.num_insns = 0;\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n+ CPUARMState *env = cpu->env_ptr;\n+ ARMCPU *arm_cpu = arm_env_get_cpu(env);\n \n dc->pc = dc->base.pc_first;\n dc->condjmp = 0;\n@@ -11240,7 +11231,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);\n dc->vec_len = 0;\n dc->vec_stride = 0;\n- dc->cp_regs = cpu->cp_regs;\n+ dc->cp_regs = arm_cpu->cp_regs;\n dc->features = env->features;\n \n /* Single step state. The code-generation logic here is:\n@@ -11265,6 +11256,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n \n init_tmp_a64_array(dc);\n \n+ return max_insns;\n+}\n+\n+void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n+ TranslationBlock *tb)\n+{\n+ CPUARMState *env = cs->env_ptr;\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ target_ulong next_page_start;\n+ int max_insns;\n+\n+ dc->base.tb = tb;\n+ dc->base.pc_first = dc->base.tb->pc;\n+ dc->base.pc_next = dc->base.pc_first;\n+ dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.num_insns = 0;\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n+\n next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n max_insns = dc->base.tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n@@ -11273,6 +11282,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n if (max_insns > TCG_MAX_INSNS) {\n max_insns = TCG_MAX_INSNS;\n }\n+ max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns);\n \n gen_tb_start(tb);\n \n","prefixes":["PULL","17/32"]}