{"id":810707,"url":"http://patchwork.ozlabs.org/api/patches/810707/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-15-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-15-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:05:54","name":"[PULL,14/32] target/i386: [tcg] Port to generic translation framework","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"06aa10042ada036d5e303d1245fce0ff06402b0a","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-15-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810707/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810707/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::22c","Subject":"[Qemu-devel] [PULL 14/32] target/i386: [tcg] Port to generic\n\ttranslation framework","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t, \tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Lluís Vilanova \n\nSigned-off-by: Lluís Vilanova \nReviewed-by: Richard Henderson \nReviewed-by: Emilio G. Cota \nTested-by: Emilio G. Cota \nMessage-Id: <150002267714.22386.5095442346868988808.stgit@frigg.lan>\nSigned-off-by: Richard Henderson \n---\n target/i386/translate.c | 106 +++++++++---------------------------------------\n 1 file changed, 19 insertions(+), 87 deletions(-)","diff":"diff --git a/target/i386/translate.c b/target/i386/translate.c\nindex ad4b2735f4..de0c989763 100644\n--- a/target/i386/translate.c\n+++ b/target/i386/translate.c\n@@ -8450,6 +8450,10 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,\n return max_insns;\n }\n \n+static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n+{\n+}\n+\n static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n {\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n@@ -8469,7 +8473,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n /* The address covered by the breakpoint must be included in\n [tb->pc, tb->pc + tb->size) in order to for it to be\n properly cleared -- thus we increment the PC here so that\n- the logic setting tb->size below does the right thing. */\n+ the generic logic setting tb->size later does the right thing. */\n dc->base.pc_next += 1;\n return true;\n } else {\n@@ -8533,94 +8537,22 @@ static void i386_tr_disas_log(const DisasContextBase *dcbase,\n log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flags);\n }\n \n-/* generate intermediate code for basic block 'tb'. */\n-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n-{\n- DisasContext dc1, *dc = &dc1;\n- int num_insns;\n- int max_insns;\n-\n- /* generate intermediate code */\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n- dc->base.tb = tb;\n- dc->base.is_jmp = DISAS_NEXT;\n- dc->base.pc_first = tb->pc;\n- dc->base.pc_next = dc->base.pc_first;\n-\n- max_insns = tb->cflags & CF_COUNT_MASK;\n- if (max_insns == 0) {\n- max_insns = CF_COUNT_MASK;\n- }\n- if (max_insns > TCG_MAX_INSNS) {\n- max_insns = TCG_MAX_INSNS;\n- }\n- max_insns = i386_tr_init_disas_context(&dc->base, cs, max_insns);\n-\n- num_insns = 0;\n- gen_tb_start(tb);\n- for(;;) {\n- i386_tr_insn_start(&dc->base, cs);\n- num_insns++;\n-\n- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n- CPUBreakpoint *bp;\n- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n- if (bp->pc == dc->base.pc_next) {\n- if (i386_tr_breakpoint_check(&dc->base, cs, bp)) {\n- break;\n- }\n- }\n- }\n-\n- if (dc->base.is_jmp == DISAS_NORETURN) {\n- break;\n- }\n- }\n-\n- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n- gen_io_start();\n- }\n-\n- i386_tr_translate_insn(&dc->base, cs);\n- /* stop translation if indicated */\n- if (dc->base.is_jmp) {\n- break;\n- }\n- /* if single step mode, we generate only one instruction and\n- generate an exception */\n- if (dc->base.singlestep_enabled) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- break;\n- }\n- /* if too long translation, stop generation too */\n- if (tcg_op_buf_full() ||\n- num_insns >= max_insns) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- break;\n- }\n- if (singlestep) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- break;\n- }\n- }\n- i386_tr_tb_stop(&dc->base, cs);\n- if (tb->cflags & CF_LAST_IO)\n- gen_io_end();\n- gen_tb_end(tb, num_insns);\n+static const TranslatorOps i386_tr_ops = {\n+ .init_disas_context = i386_tr_init_disas_context,\n+ .tb_start = i386_tr_tb_start,\n+ .insn_start = i386_tr_insn_start,\n+ .breakpoint_check = i386_tr_breakpoint_check,\n+ .translate_insn = i386_tr_translate_insn,\n+ .tb_stop = i386_tr_tb_stop,\n+ .disas_log = i386_tr_disas_log,\n+};\n \n- tb->size = dc->base.pc_next - dc->base.pc_first;\n- tb->icount = num_insns;\n+/* generate intermediate code for basic block 'tb'. */\n+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)\n+{\n+ DisasContext dc;\n \n-#ifdef DEBUG_DISAS\n- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)\n- && qemu_log_in_addr_range(dc->base.pc_first)) {\n- qemu_log_lock();\n- qemu_log(\"----------------\\n\");\n- i386_tr_disas_log(&dc->base, cs);\n- qemu_log(\"\\n\");\n- qemu_log_unlock();\n- }\n-#endif\n+ translator_loop(&i386_tr_ops, &dc.base, cpu, tb);\n }\n \n void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,\n","prefixes":["PULL","14/32"]}