{"id":810706,"url":"http://patchwork.ozlabs.org/api/patches/810706/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-25-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-25-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:06:04","name":"[PULL,24/32] target/arm: [tcg] Port to tb_stop","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0db7dd341b178b9bbcb399456f873312fefa7eaf","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-25-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810706/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810706/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c05::235","Subject":"[Qemu-devel] [PULL 24/32] target/arm: [tcg] Port to tb_stop","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t, \tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Lluís Vilanova \n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nReviewed-by: Emilio G. Cota \nSigned-off-by: Lluís Vilanova \nMessage-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan>\nSigned-off-by: Richard Henderson \n---\n target/arm/translate.c | 161 ++++++++++++++++++++++++++-----------------------\n 1 file changed, 84 insertions(+), 77 deletions(-)","diff":"diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 5737299943..10527b50c8 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -12057,85 +12057,13 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n dc->base.pc_next = dc->pc;\n }\n \n-/* generate intermediate code for basic block 'tb'. */\n-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n {\n- DisasContext dc1, *dc = &dc1;\n- int max_insns;\n-\n- /* generate intermediate code */\n-\n- /* The A64 decoder has its own top level loop, because it doesn't need\n- * the A32/T32 complexity to do with conditional execution/IT blocks/etc.\n- */\n- if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {\n- gen_intermediate_code_a64(&dc->base, cs, tb);\n- return;\n- }\n-\n- dc->base.tb = tb;\n- dc->base.pc_first = dc->base.tb->pc;\n- dc->base.pc_next = dc->base.pc_first;\n- dc->base.is_jmp = DISAS_NEXT;\n- dc->base.num_insns = 0;\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n-\n- max_insns = tb->cflags & CF_COUNT_MASK;\n- if (max_insns == 0) {\n- max_insns = CF_COUNT_MASK;\n- }\n- if (max_insns > TCG_MAX_INSNS) {\n- max_insns = TCG_MAX_INSNS;\n- }\n- max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns);\n-\n- gen_tb_start(tb);\n-\n- tcg_clear_temp_count();\n- arm_tr_tb_start(&dc->base, cs);\n-\n- do {\n- dc->base.num_insns++;\n- arm_tr_insn_start(&dc->base, cs);\n-\n- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n- CPUBreakpoint *bp;\n- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n- if (bp->pc == dc->base.pc_next) {\n- if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {\n- break;\n- }\n- }\n- }\n- if (dc->base.is_jmp > DISAS_TOO_MANY) {\n- break;\n- }\n- }\n-\n- if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n- gen_io_start();\n- }\n-\n- arm_tr_translate_insn(&dc->base, cs);\n-\n- if (tcg_check_temp_count()) {\n- fprintf(stderr, \"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n- dc->pc);\n- }\n-\n- if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep ||\n- dc->base.num_insns >= max_insns)) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- }\n- } while (!dc->base.is_jmp);\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n \n- if (tb->cflags & CF_LAST_IO) {\n- if (dc->condjmp) {\n- /* FIXME: This can theoretically happen with self-modifying\n- code. */\n- cpu_abort(cs, \"IO on conditional branch instruction\");\n- }\n- gen_io_end();\n+ if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) {\n+ /* FIXME: This can theoretically happen with self-modifying code. */\n+ cpu_abort(cpu, \"IO on conditional branch instruction\");\n }\n \n /* At this stage dc->condjmp will only be set when the skipped\n@@ -12241,6 +12169,85 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n gen_goto_tb(dc, 1, dc->pc);\n }\n }\n+}\n+\n+/* generate intermediate code for basic block 'tb'. */\n+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+{\n+ DisasContext dc1, *dc = &dc1;\n+ int max_insns;\n+\n+ /* generate intermediate code */\n+\n+ /* The A64 decoder has its own top level loop, because it doesn't need\n+ * the A32/T32 complexity to do with conditional execution/IT blocks/etc.\n+ */\n+ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {\n+ gen_intermediate_code_a64(&dc->base, cs, tb);\n+ return;\n+ }\n+\n+ dc->base.tb = tb;\n+ dc->base.pc_first = dc->base.tb->pc;\n+ dc->base.pc_next = dc->base.pc_first;\n+ dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.num_insns = 0;\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n+\n+ max_insns = tb->cflags & CF_COUNT_MASK;\n+ if (max_insns == 0) {\n+ max_insns = CF_COUNT_MASK;\n+ }\n+ if (max_insns > TCG_MAX_INSNS) {\n+ max_insns = TCG_MAX_INSNS;\n+ }\n+ max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns);\n+\n+ gen_tb_start(tb);\n+\n+ tcg_clear_temp_count();\n+ arm_tr_tb_start(&dc->base, cs);\n+\n+ do {\n+ dc->base.num_insns++;\n+ arm_tr_insn_start(&dc->base, cs);\n+\n+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n+ CPUBreakpoint *bp;\n+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n+ if (bp->pc == dc->base.pc_next) {\n+ if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {\n+ break;\n+ }\n+ }\n+ }\n+ if (dc->base.is_jmp > DISAS_TOO_MANY) {\n+ break;\n+ }\n+ }\n+\n+ if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n+ gen_io_start();\n+ }\n+\n+ arm_tr_translate_insn(&dc->base, cs);\n+\n+ if (tcg_check_temp_count()) {\n+ fprintf(stderr, \"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n+ dc->pc);\n+ }\n+\n+ if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep ||\n+ dc->base.num_insns >= max_insns)) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n+ } while (!dc->base.is_jmp);\n+\n+ if (dc->base.tb->cflags & CF_LAST_IO) {\n+ gen_io_end();\n+ }\n+\n+ arm_tr_tb_stop(&dc->base, cs);\n \n gen_tb_end(tb, dc->base.num_insns);\n \n","prefixes":["PULL","24/32"]}