{"id":810698,"url":"http://patchwork.ozlabs.org/api/patches/810698/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-21-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-21-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:06:00","name":"[PULL,20/32] target/arm: [tcg, a64] Port to insn_start","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"55c35dc0220ecb32062bf7288d8e509f49d24a53","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-21-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810698/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810698/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::233","Subject":"[Qemu-devel] [PULL 20/32] target/arm: [tcg, a64] Port to insn_start","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t, \tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Lluís Vilanova \n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova \nReviewed-by: Richard Henderson \nReviewed-by: Alex Benneé \nMessage-Id: <150002413187.22386.156315485813606121.stgit@frigg.lan>\n[rth: Use DISAS_TOO_MANY for \"execute only one more\" after bp.]\nSigned-off-by: Richard Henderson \n---\n target/arm/translate-a64.c | 11 ++++++++--\n target/arm/translate.c | 55 +++++++++++++++++++++++++++++-----------------\n 2 files changed, 44 insertions(+), 22 deletions(-)","diff":"diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex e8dc96c28a..1eab10696c 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -11259,6 +11259,14 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n return max_insns;\n }\n \n+static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+\n+ dc->insn_start_idx = tcg_op_buf_count();\n+ tcg_gen_insn_start(dc->pc, 0, 0);\n+}\n+\n void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n TranslationBlock *tb)\n {\n@@ -11290,8 +11298,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n \n do {\n dc->base.num_insns++;\n- dc->insn_start_idx = tcg_op_buf_count();\n- tcg_gen_insn_start(dc->pc, 0, 0);\n+ aarch64_tr_insn_start(&dc->base, cs);\n \n if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n CPUBreakpoint *bp;\ndiff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 005157225c..2f5f65310d 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11946,6 +11946,33 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n 0);\n }\n \n+static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n+ const CPUBreakpoint *bp)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+\n+ if (bp->flags & BP_CPU) {\n+ gen_set_condexec(dc);\n+ gen_set_pc_im(dc, dc->pc);\n+ gen_helper_check_breakpoints(cpu_env);\n+ /* End the TB early; it's likely not going to be executed */\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ } else {\n+ gen_exception_internal_insn(dc, 0, EXCP_DEBUG);\n+ /* The address covered by the breakpoint must be\n+ included in [tb->pc, tb->pc + tb->size) in order\n+ to for it to be properly cleared -- thus we\n+ increment the PC here so that the logic setting\n+ tb->size below does the right thing. */\n+ /* TODO: Advance PC by correct instruction length to\n+ * avoid disassembler error messages */\n+ dc->pc += 2;\n+ dc->base.is_jmp = DISAS_NORETURN;\n+ }\n+\n+ return true;\n+}\n+\n /* generate intermediate code for basic block 'tb'. */\n void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n {\n@@ -11994,28 +12021,15 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n CPUBreakpoint *bp;\n QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n- if (bp->pc == dc->pc) {\n- if (bp->flags & BP_CPU) {\n- gen_set_condexec(dc);\n- gen_set_pc_im(dc, dc->pc);\n- gen_helper_check_breakpoints(cpu_env);\n- /* End the TB early; it's likely not going to be executed */\n- dc->base.is_jmp = DISAS_UPDATE;\n- } else {\n- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);\n- /* The address covered by the breakpoint must be\n- included in [tb->pc, tb->pc + tb->size) in order\n- to for it to be properly cleared -- thus we\n- increment the PC here so that the logic setting\n- tb->size below does the right thing. */\n- /* TODO: Advance PC by correct instruction length to\n- * avoid disassembler error messages */\n- dc->pc += 2;\n- goto done_generating;\n+ if (bp->pc == dc->base.pc_next) {\n+ if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {\n+ break;\n }\n- break;\n }\n }\n+ if (dc->base.is_jmp > DISAS_TOO_MANY) {\n+ break;\n+ }\n }\n \n if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n@@ -12137,6 +12151,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n gen_exception(EXCP_SMC, syn_aa32_smc(), 3);\n break;\n case DISAS_NEXT:\n+ case DISAS_TOO_MANY:\n case DISAS_UPDATE:\n gen_set_pc_im(dc, dc->pc);\n /* fall through */\n@@ -12158,6 +12173,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n */\n switch(dc->base.is_jmp) {\n case DISAS_NEXT:\n+ case DISAS_TOO_MANY:\n gen_goto_tb(dc, 1, dc->pc);\n break;\n case DISAS_JUMP:\n@@ -12211,7 +12227,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n }\n }\n \n-done_generating:\n gen_tb_end(tb, dc->base.num_insns);\n \n #ifdef DEBUG_DISAS\n","prefixes":["PULL","20/32"]}