{"id":810667,"url":"http://patchwork.ozlabs.org/api/patches/810667/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/562b37aa-4873-1704-b067-7b7010e9bb0c@foss.arm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<562b37aa-4873-1704-b067-7b7010e9bb0c@foss.arm.com>","list_archive_url":null,"date":"2017-09-06T15:15:50","name":"[arm-embedded,GCC/ARM] Rewire -mfpu=fp-armv8 as VFPv5 + D32 + DP","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bea9f7413ffef0e25a27e19cf800addf10e8c2d3","submitter":{"id":67886,"url":"http://patchwork.ozlabs.org/api/people/67886/?format=json","name":"Thomas Preudhomme","email":"thomas.preudhomme@foss.arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/562b37aa-4873-1704-b067-7b7010e9bb0c@foss.arm.com/mbox/","series":[{"id":1832,"url":"http://patchwork.ozlabs.org/api/series/1832/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=1832","date":"2017-09-06T15:15:50","name":"[arm-embedded,GCC/ARM] Rewire -mfpu=fp-armv8 as VFPv5 + D32 + DP","version":1,"mbox":"http://patchwork.ozlabs.org/series/1832/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810667/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810667/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461619-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"g8m12fdT\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnRxL4vxMz9t2R\n\tfor ;\n\tThu, 7 Sep 2017 01:16:06 +1000 (AEST)","(qmail 3093 invoked by alias); 6 Sep 2017 15:15:58 -0000","(qmail 3075 invoked by uid 89); 6 Sep 2017 15:15:57 -0000","from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com)\n\t(217.140.101.70) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tWed, 06 Sep 2017 15:15:55 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\tby\n\tusa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id\n\tDBC0D15AD\tfor ;\n\tWed, 6 Sep 2017 08:15:52 -0700 (PDT)","from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\tby usa-sjc-imap-foss1.foss.arm.com (Postfix)\n\twith ESMTPSA id 49B723F578\tfor ;\n\tWed, 6 Sep 2017 08:15:52 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:references:subject:to:from:message-id:date:mime-version\n\t:in-reply-to:content-type; q=dns; s=default; b=aQiu42VjNizI+nHce\n\tRvcfT6//khjNtvpW21AxC5Jod/X6B3RCPJ/ZSFvlsRU4xs6h5IiOcETeMROinSxF\n\tzPvJp3MXOxGGAggQLenwkbz0PSG5j/uappUGAPHrGdDyMkFdWVNu/Lm/x9oOePUT\n\tQNTlnM1I64wScemoRc1cabWmqQ=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:references:subject:to:from:message-id:date:mime-version\n\t:in-reply-to:content-type; s=default; bh=tDTz6yeZsZZOyO9JROEa9Bu\n\t6N9k=; b=g8m12fdTlhZ0InSc6JS2LDtg5MLGyLf/kvJ03yX/4zDg2NlTyScpxNH\n\toMCeih3UwES45q7y3oa0DthgdSOBX7tSov81UhgXoDgOZblTM3SFx8ZKjvsqY37P\n\t7ikZS42Nm0xfvQRHaJ49T3GII6Z25bTCr0fojFUwqW5dB8ciApzc=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-25.7 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","References":"<0f5ce400-4f25-9373-2cc7-3a473e089a12@foss.arm.com>","Subject":"[arm-embedded] [PATCH,\n\tGCC/ARM] Rewire -mfpu=fp-armv8 as VFPv5 + D32 + DP","To":"\"gcc-patches@gcc.gnu.org\" ","From":"Thomas Preudhomme ","X-Forwarded-Message-Id":"<0f5ce400-4f25-9373-2cc7-3a473e089a12@foss.arm.com>","Message-ID":"<562b37aa-4873-1704-b067-7b7010e9bb0c@foss.arm.com>","Date":"Wed, 6 Sep 2017 16:15:50 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:52.0) Gecko/20100101 Thunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<0f5ce400-4f25-9373-2cc7-3a473e089a12@foss.arm.com>","Content-Type":"multipart/mixed;\n\tboundary=\"------------3361D9436F4F42524254C5A4\"","X-IsSubscribed":"yes"},"content":"Hi,\n\nWe have decided to apply the following patch to the embedded-7-branch to enable \nARMv8-R support.\n\n\nChangeLog entry is as follows:\n\n*** gcc/ChangeLog.arm ***\n\n2017-09-04 Thomas Preud'homme \n\n Backport from mainline\n 2017-07-14 Thomas Preud'homme \n\n * config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator.\n (ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32.\n * config/arm/arm-cpus.in (armv8-r): Define fp.sp as enabling FPv5.\n (fp-armv8): Define it as FP_ARMv8 only.\n config/arm/arm.h (TARGET_FPU_ARMV8): Delete.\n (TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than\n TARGET_FPU_ARMV8.\n config/arm/arm.c (arm_rtx_costs_internal): Replace checks against\n TARGET_FPU_ARMV8 by checks against TARGET_VFP5.\n * config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define\n first ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather\n than TARGET_FPU_ARMV8.\n * config/arm/arm-c.c (arm_cpu_builtins): Likewise for\n __ARM_FEATURE_NUMERIC_MAXMIN macro definition.\n * config/arm/arm.md (cmov): Condition on TARGET_VFP5 rather than\n TARGET_FPU_ARMV8.\n * config/arm/neon.md (neon_vrint): Likewise.\n (neon_vcvt): Likewise.\n (neon_): Likewise.\n (3): Likewise.\n * config/arm/vfp.md (lsi2): Likewise.\n * config/arm/predicates.md (arm_cond_move_operator): Check against\n TARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing.\n\nBest regards,\n\nThomas\nHi,\n\nfp-armv8 is currently defined as a double precision FPv5 with 32 D\nregisters *and* a special FP_ARMv8 bit. However FP for ARMv8 should only\nbring 32 D registers on top of FPv5-D16 so this FP_ARMv8 bit is\nspurious. As a consequence, many instruction patterns which are guarded\nby TARGET_FPU_ARMV8 are unavailable to FPv5-D16 and FPv5-SP-D16.\n\nThis patch gets rid of TARGET_FPU_ARMV8 and rewire all uses to\nexpressions based on TARGET_VFP5, TARGET_VFPD32 and TARGET_VFP_DOUBLE.\nIt also redefine ISA_FP_ARMv8 to include the D32 capability to\ndistinguish it from FPv5-D16. At last, it sets the +fp.sp for ARMv8-R to\nenable FPv5-SP-D16 (ie FP for ARMv8 with single precision only and 16 D\nregisters).\n\nChangeLog entry is as follows:\n\n2017-07-07 Thomas Preud'homme \n\n\t* config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator.\n\t(ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32.\n\t* config/arm/arm-cpus.in (armv8-r): Define fp.sp as enabling FPv5.\n\t(fp-armv8): Define it as FP_ARMv8 only.\n\tconfig/arm/arm.h (TARGET_FPU_ARMV8): Delete.\n\t(TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than\n\tTARGET_FPU_ARMV8.\n\tconfig/arm/arm.c (arm_rtx_costs_internal): Replace checks against\n\tTARGET_FPU_ARMV8 by checks against TARGET_VFP5.\n\t* config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define\n\tfirst ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather\n\tthan TARGET_FPU_ARMV8.\n\t* config/arm/arm-c.c (arm_cpu_builtins): Likewise for\n\t__ARM_FEATURE_NUMERIC_MAXMIN macro definition.\n\t* config/arm/arm.md (cmov): Condition on TARGET_VFP5 rather than\n\tTARGET_FPU_ARMV8.\n\t* config/arm/neon.md (neon_vrint): Likewise.\n\t(neon_vcvt): Likewise.\n\t(neon_): Likewise.\n\t(3): Likewise.\n\t* config/arm/vfp.md (lsi2): Likewise.\n\t* config/arm/predicates.md (arm_cond_move_operator): Check against\n\tTARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing.\n\nTesting:\n * Bootstrapped under ARMv8-A Thumb state and ran testsuite -> no regression\n * built Spec2000 and Spec2006 with -march=armv8-a+fp16 and compared objdump \n-> no code generation difference\n\nIs this ok for trunk?\n\nBest regards,\n\nThomas","diff":"diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c\nindex 63ee880822c17eda55dd58438d61cbbba333b2c6..7504ed581c63a657a0dff48442633704bd252b2e 100644\n--- a/gcc/config/arm/arm-builtins.c\n+++ b/gcc/config/arm/arm-builtins.c\n@@ -3098,7 +3098,7 @@ arm_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in)\n NULL_TREE is returned if no such builtin is available. */\n #undef ARM_CHECK_BUILTIN_MODE\n #define ARM_CHECK_BUILTIN_MODE(C) \\\n- (TARGET_FPU_ARMV8 \\\n+ (TARGET_VFP5 \\\n && flag_unsafe_math_optimizations \\\n && ARM_CHECK_BUILTIN_MODE_1 (C))\n \ndiff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c\nindex a3daa3220a2bc4220dffdb7ca08ca9419bdac425..9178937b6d9e0fe5d0948701390c4cf01f4f8c7d 100644\n--- a/gcc/config/arm/arm-c.c\n+++ b/gcc/config/arm/arm-c.c\n@@ -96,7 +96,7 @@ arm_cpu_builtins (struct cpp_reader* pfile)\n \t\t || TARGET_ARM_ARCH_ISA_THUMB >=2));\n \n def_or_undef_macro (pfile, \"__ARM_FEATURE_NUMERIC_MAXMIN\",\n-\t\t TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_FPU_ARMV8);\n+\t\t TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_VFP5);\n \n def_or_undef_macro (pfile, \"__ARM_FEATURE_SIMD32\", TARGET_INT_SIMD);\n \ndiff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in\nindex f35128acb7d68c6a0592355b9d3d56ee8f826aca..e2ff297aed7514073dbb3bf5ee86964f202e5a14 100644\n--- a/gcc/config/arm/arm-cpus.in\n+++ b/gcc/config/arm/arm-cpus.in\n@@ -389,7 +389,7 @@ begin arch armv8-r\n option crc add bit_crc32\n # fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision\n # note: no fp option for fp-armv8 (d16) + double precision at the moment\n- option fp.sp add FP_ARMv8\n+ option fp.sp add FPv5\n option simd add FP_ARMv8 NEON\n option crypto add FP_ARMv8 CRYPTO\n option nocrypto remove ALL_CRYPTO\n@@ -1390,7 +1390,7 @@ begin fpu fpv5-d16\n end fpu fpv5-d16\n \n begin fpu fp-armv8\n- isa FP_ARMv8 FP_D32\n+ isa FP_ARMv8\n end fpu fp-armv8\n \n begin fpu neon-fp-armv8\ndiff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h\nindex 0d66a0400c517668db023fc66ff43e26d43add51..dbd29eaa52f2007498c2aff6263b8b6c3a70e2c2 100644\n--- a/gcc/config/arm/arm-isa.h\n+++ b/gcc/config/arm/arm-isa.h\n@@ -60,7 +60,6 @@ enum isa_feature\n isa_bit_VFPv4,\t/* Vector floating point v4. */\n isa_bit_FPv5,\t/* Floating point v5. */\n isa_bit_lpae,\t/* ARMv7-A LPAE. */\n- isa_bit_FP_ARMv8,\t/* ARMv8 floating-point extension. */\n isa_bit_neon,\t/* Advanced SIMD instructions. */\n isa_bit_fp16conv,\t/* Conversions to/from fp16 (VFPv3 extension). */\n isa_bit_fp_dbl,\t/* Double precision operations supported. */\n@@ -143,7 +142,7 @@ enum isa_feature\n default. isa_bit_fp16 is deliberately missing from this list. */\n #define ISA_ALL_FPU_INTERNAL\t\t\t\t\t\t\\\n isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, isa_bit_FPv5,\t\t\\\n- isa_bit_FP_ARMv8, isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD\n+ isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD\n \n /* Similarly, but including fp16 and other extensions that aren't part of\n -mfpu support. */\n@@ -154,10 +153,10 @@ enum isa_feature\n #define ISA_VFPv3\tISA_VFPv2, isa_bit_VFPv3\n #define ISA_VFPv4\tISA_VFPv3, isa_bit_VFPv4, isa_bit_fp16conv\n #define ISA_FPv5\tISA_VFPv4, isa_bit_FPv5\n-#define ISA_FP_ARMv8\tISA_FPv5, isa_bit_FP_ARMv8\n \n #define ISA_FP_DBL\tisa_bit_fp_dbl\n #define ISA_FP_D32\tISA_FP_DBL, isa_bit_fp_d32\n+#define ISA_FP_ARMv8\tISA_FPv5, ISA_FP_D32\n #define ISA_NEON\tISA_FP_D32, isa_bit_neon\n #define ISA_CRYPTO\tISA_NEON, isa_bit_crypto\n \ndiff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h\nindex 315622212a5ce10d0c771535fe31f63c3be16444..4f53583cf0219de4329bc64a47a5a42c550ff354 100644\n--- a/gcc/config/arm/arm.h\n+++ b/gcc/config/arm/arm.h\n@@ -196,10 +196,6 @@ extern tree arm_fp16_type_node;\n /* FPU supports fused-multiply-add operations. */\n #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv4))\n \n-/* FPU is ARMv8 compatible. */\n-#define TARGET_FPU_ARMV8\t\t\t\t\t\\\n- (bitmap_bit_p (arm_active_target.isa, isa_bit_FP_ARMv8))\n-\n /* FPU supports Crypto extensions. */\n #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto))\n \n@@ -216,7 +212,7 @@ extern tree arm_fp16_type_node;\n \n /* FPU supports the floating point FP16 instructions for ARMv8.2 and later. */\n #define TARGET_VFP_FP16INST \\\n- (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 && arm_fp16_inst)\n+ (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst)\n \n /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */\n #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA)\ndiff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\nindex c6101efd555996a4c6db5eaea0130b0940c4cff8..f59132c3f079d10d9e3d920b61037db2f3144eee 100644\n--- a/gcc/config/arm/arm.c\n+++ b/gcc/config/arm/arm.c\n@@ -10755,7 +10755,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,\n \t{\n \t if (speed_p)\n \t *cost += extra_cost->fp[mode == DFmode].widen;\n-\t if (!TARGET_FPU_ARMV8\n+\t if (!TARGET_VFP5\n \t && GET_MODE (XEXP (x, 0)) == HFmode)\n \t {\n \t /* Pre v8, widening HF->DF is a two-step process, first\n@@ -10849,7 +10849,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,\n \t return true;\n \t }\n \t else if (GET_MODE_CLASS (mode) == MODE_FLOAT\n-\t\t && TARGET_FPU_ARMV8)\n+\t\t && TARGET_VFP5)\n \t {\n \t if (speed_p)\n \t\t*cost += extra_cost->fp[mode == DFmode].roundint;\ndiff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md\nindex e6e1ac54a850c35807d683804f5294fbef1487ad..049a78edefe9f85c6f84a4ecf0158d559e1d5674 100644\n--- a/gcc/config/arm/arm.md\n+++ b/gcc/config/arm/arm.md\n@@ -7879,7 +7879,7 @@\n \t\t\t \"\")\n \t\t\t (match_operand:SDF 4 \"s_register_operand\"\n \t\t\t \"\")))]\n- \"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 \"\n+ \"TARGET_HARD_FLOAT && TARGET_VFP5 \"\n \"*\n {\n enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]);\ndiff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md\nindex 33b25ff3c730544b4376bf318400d703c8813a0a..235c46da1a19712e2924d748545474ed991d9f92 100644\n--- a/gcc/config/arm/neon.md\n+++ b/gcc/config/arm/neon.md\n@@ -751,7 +751,7 @@\n (unspec:VCVTF [(match_operand:VCVTF 1\n \t\t \"s_register_operand\" \"w\")]\n \t\tNEON_VRINT))]\n- \"TARGET_NEON && TARGET_FPU_ARMV8\"\n+ \"TARGET_NEON && TARGET_VFP5\"\n \"vrint.f32\\\\t%0, %1\"\n [(set_attr \"type\" \"neon_fp_round_\")]\n )\n@@ -761,7 +761,7 @@\n \t(FIXUORS: (unspec:VCVTF\n \t\t\t [(match_operand:VCVTF 1 \"register_operand\" \"w\")]\n \t\t\t NEON_VCVT)))]\n- \"TARGET_NEON && TARGET_FPU_ARMV8\"\n+ \"TARGET_NEON && TARGET_VFP5\"\n \"vcvt.32.f32\\\\t%0, %1\"\n [(set_attr \"type\" \"neon_fp_to_int_\")\n (set_attr \"predicable\" \"no\")]\n@@ -2901,7 +2901,7 @@\n \t(unspec:VCVTF [(match_operand:VCVTF 1 \"s_register_operand\" \"w\")\n \t\t (match_operand:VCVTF 2 \"s_register_operand\" \"w\")]\n \t\t VMAXMINFNM))]\n- \"TARGET_NEON && TARGET_FPU_ARMV8\"\n+ \"TARGET_NEON && TARGET_VFP5\"\n \".\\t%0, %1, %2\"\n [(set_attr \"type\" \"neon_fp_minmax_s\")]\n )\n@@ -2912,7 +2912,7 @@\n \t(unspec:VCVTF [(match_operand:VCVTF 1 \"s_register_operand\" \"w\")\n \t\t (match_operand:VCVTF 2 \"s_register_operand\" \"w\")]\n \t\t VMAXMINFNM))]\n- \"TARGET_NEON && TARGET_FPU_ARMV8\"\n+ \"TARGET_NEON && TARGET_VFP5\"\n \".\\t%0, %1, %2\"\n [(set_attr \"type\" \"neon_fp_minmax_s\")]\n )\ndiff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md\nindex afb5d6339a8af362384c93bbb46928635073b74b..3e25cd16b29231d53b4cadce3db0fbb3168cd4c5 100644\n--- a/gcc/config/arm/predicates.md\n+++ b/gcc/config/arm/predicates.md\n@@ -350,9 +350,9 @@\n \n (define_special_predicate \"arm_cond_move_operator\"\n (if_then_else (match_test \"arm_restrict_it\")\n- (and (match_test \"TARGET_FPU_ARMV8\")\n- (match_operand 0 \"arm_vsel_comparison_operator\"))\n- (match_operand 0 \"expandable_comparison_operator\")))\n+\t\t(and (match_test \"TARGET_VFP5\")\n+\t\t (match_operand 0 \"arm_vsel_comparison_operator\"))\n+\t\t(match_operand 0 \"expandable_comparison_operator\")))\n \n (define_special_predicate \"noov_comparison_operator\"\n (match_code \"lt,ge,eq,ne\"))\ndiff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md\nindex d8f77e2ffe4fdb7c952d6a5ac947d91f89ce259d..23c1d67c9e3707e64a4e206dc62727e4c79ba89c 100644\n--- a/gcc/config/arm/vfp.md\n+++ b/gcc/config/arm/vfp.md\n@@ -1997,7 +1997,7 @@\n (FIXUORS:SI (unspec:SDF\n [(match_operand:SDF 1\n \"register_operand\" \"\")] VCVT)))]\n- \"TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 \"\n+ \"TARGET_HARD_FLOAT && TARGET_VFP5 \"\n \"vcvt.32.\\\\t%0, %1\"\n [(set_attr \"predicable\" \"no\")\n (set_attr \"conds\" \"unconditional\")\n","prefixes":["arm-embedded","GCC/ARM"]}