{"id":810665,"url":"http://patchwork.ozlabs.org/api/patches/810665/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/059cae6c-9591-9dd1-6a73-773e70fbc8d6@foss.arm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<059cae6c-9591-9dd1-6a73-773e70fbc8d6@foss.arm.com>","list_archive_url":null,"date":"2017-09-06T15:12:44","name":"[arm-embedded,1/3,GCC/ARM,ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"dd0d58b10b507cb27802e244fff46d47a2c5faf4","submitter":{"id":67886,"url":"http://patchwork.ozlabs.org/api/people/67886/?format=json","name":"Thomas Preudhomme","email":"thomas.preudhomme@foss.arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/059cae6c-9591-9dd1-6a73-773e70fbc8d6@foss.arm.com/mbox/","series":[{"id":1831,"url":"http://patchwork.ozlabs.org/api/series/1831/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=1831","date":"2017-09-06T15:12:44","name":"[arm-embedded,1/3,GCC/ARM,ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8","version":1,"mbox":"http://patchwork.ozlabs.org/series/1831/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810665/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810665/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461617-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"BHjbNhUt\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnRsm3ZzGz9t50\n\tfor ;\n\tThu, 7 Sep 2017 01:12:58 +1000 (AEST)","(qmail 129160 invoked by alias); 6 Sep 2017 15:12:50 -0000","(qmail 129150 invoked by uid 89); 6 Sep 2017 15:12:49 -0000","from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com)\n\t(217.140.101.70) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tWed, 06 Sep 2017 15:12:48 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\tby\n\tusa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id\n\tAFE0415AD\tfor ;\n\tWed, 6 Sep 2017 08:12:46 -0700 (PDT)","from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\tby usa-sjc-imap-foss1.foss.arm.com (Postfix)\n\twith ESMTPSA id 116743F578\tfor ;\n\tWed, 6 Sep 2017 08:12:45 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:references:subject:to:from:message-id:date:mime-version\n\t:in-reply-to:content-type; q=dns; s=default; b=i0THGAOuVFwaJvxix\n\tAP1YY2Dn5NtLQKo9yYi2LyfkeMpnOQVUvDpd7D+hKOVg9Up0lJ7kAWuNE+AWwuB9\n\tXXlU9vzuphVv8xu6YX6xSgixYgn+QpYAD2DARKfP417Vzoefo+4gq3KksRcJyG4H\n\tyZvp9RtwO8CKWXd/yqQkY8otsc=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:references:subject:to:from:message-id:date:mime-version\n\t:in-reply-to:content-type; s=default; bh=pT+2ddohZKvZTZGYMjVxl9R\n\tZKBc=; b=BHjbNhUtkbdgrH/Oreu4sjbDJFEAUFjxMCNH8GqGf6tSEAes/SkusuX\n\tevjyBl08xUkRb7Lv8HfA9ijg4cTqnRXj41caGMOy15wqfIFF2pACBqJaEao5LZj0\n\tfoDIOzaUasKFbl6W16pJYFwewvngAV4sKT8uCpCHkhAQYnMMR3oU=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=processors,\n\tBest","X-HELO":"foss.arm.com","References":"<88ba1e93-952e-0759-9bca-ad120fff18f4@foss.arm.com>","Subject":"[arm-embedded] [PATCH 1/3, GCC/ARM,\n\tping] Add MIDR info for ARM Cortex-R7 and Cortex-R8","To":"\"gcc-patches@gcc.gnu.org\" ","From":"Thomas Preudhomme ","X-Forwarded-Message-Id":"<88ba1e93-952e-0759-9bca-ad120fff18f4@foss.arm.com>","Message-ID":"<059cae6c-9591-9dd1-6a73-773e70fbc8d6@foss.arm.com>","Date":"Wed, 6 Sep 2017 16:12:44 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:52.0) Gecko/20100101 Thunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<88ba1e93-952e-0759-9bca-ad120fff18f4@foss.arm.com>","Content-Type":"multipart/mixed;\n\tboundary=\"------------C0584B09365286F38B1B0F96\"","X-IsSubscribed":"yes"},"content":"Hi,\n\nWe have decided to apply the following patch to the embedded-7-branch as a \ndependency patch to enable ARMv8-R support.\n\nChangeLog entry is as follows:\n\n*** gcc/ChangeLog.arm ***\n\n2017-09-04 Thomas Preud'homme \n\n Backport from mainline\n 2017-07-04 Thomas Preud'homme \n\n * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM\n Cortex-R7 and Cortex-R8 processors.\n\nBest regards,\n\nThomas\nPing?\n\nBest regards,\n\nThomas\n\nOn 29/06/17 14:55, Thomas Preudhomme wrote:\n> Hi,\n> \n> The driver is missing MIDR information for processors ARM Cortex-R7 and\n> Cortex-R8 to support -march/-mcpu/-mtune=native on the command line.\n> This patch adds the missing information.\n> \n> ChangeLog entry is as follows:\n> \n> *** gcc/ChangeLog ***\n> \n> 2017-01-31 Thomas Preud'homme \n> \n> * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM\n> Cortex-R7 and Cortex-R8 processors.\n> \n> Is this ok for master?\n> \n> Best regards,\n> \n> Thomas","diff":"diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c\nindex b034f13fda63f5892bbd9879d72f4b02e2632d69..29873d57a1e45fd989f6ff01dd4a2ae7320d93bb 100644\n--- a/gcc/config/arm/driver-arm.c\n+++ b/gcc/config/arm/driver-arm.c\n@@ -54,6 +54,8 @@ static struct vendor_cpu arm_cpu_table[] = {\n {\"0xd09\", \"armv8-a+crc\", \"cortex-a73\"},\n {\"0xc14\", \"armv7-r\", \"cortex-r4\"},\n {\"0xc15\", \"armv7-r\", \"cortex-r5\"},\n+ {\"0xc17\", \"armv7-r\", \"cortex-r7\"},\n+ {\"0xc18\", \"armv7-r\", \"cortex-r8\"},\n {\"0xc20\", \"armv6-m\", \"cortex-m0\"},\n {\"0xc21\", \"armv6-m\", \"cortex-m1\"},\n {\"0xc23\", \"armv7-m\", \"cortex-m3\"},\n","prefixes":["arm-embedded","1/3","GCC/ARM","ping"]}