{"id":810660,"url":"http://patchwork.ozlabs.org/api/patches/810660/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-13-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906144940.30880-13-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T14:49:38","name":"[PULL,12/14] tcg/s390: Use distinct-operands facility","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"800c98cfac233bc882b1c8f1982872d057afda7c","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-13-richard.henderson@linaro.org/mbox/","series":[{"id":1829,"url":"http://patchwork.ozlabs.org/api/series/1829/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1829","date":"2017-09-06T14:49:28","name":"[PULL,01/14] tcg: Remove support for ia64 as host","version":1,"mbox":"http://patchwork.ozlabs.org/series/1829/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810660/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810660/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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This needs an extra move. */\n- tcg_out_mov(s, type, TCG_TMP0, c1);\n+ instead of COMPARE LOGICAL. This may need an extra move. */\n if (c2const) {\n- tcg_out_movi(s, TCG_TYPE_I64, dest, 0);\n+ tcg_out_mov(s, type, TCG_TMP0, c1);\n if (type == TCG_TYPE_I32) {\n tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2);\n } else {\n tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2);\n }\n+ } else if (s390_facilities & FACILITY_DISTINCT_OPS) {\n+ if (type == TCG_TYPE_I32) {\n+ tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2);\n+ } else {\n+ tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2);\n+ }\n } else {\n+ tcg_out_mov(s, type, TCG_TMP0, c1);\n if (type == TCG_TYPE_I32) {\n tcg_out_insn(s, RR, SLR, TCG_TMP0, c2);\n } else {\n tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2);\n }\n- tcg_out_movi(s, TCG_TYPE_I64, dest, 0);\n }\n+ tcg_out_movi(s, TCG_TYPE_I64, dest, 0);\n tcg_out_insn(s, RRE, ALCGR, dest, dest);\n return;\n \n@@ -1648,7 +1667,7 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,\n static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n const TCGArg *args, const int *const_args)\n {\n- S390Opcode op;\n+ S390Opcode op, op2;\n TCGArg a0, a1, a2;\n \n switch (opc) {\n@@ -1753,29 +1772,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n if (const_args[2]) {\n a2 = -a2;\n goto do_addi_32;\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RR, SR, a0, a2);\n+ } else {\n+ tcg_out_insn(s, RRF, SRK, a0, a1, a2);\n }\n- tcg_out_insn(s, RR, SR, args[0], args[2]);\n break;\n \n case INDEX_op_and_i32:\n+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];\n if (const_args[2]) {\n- tgen_andi(s, TCG_TYPE_I32, args[0], args[2]);\n+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);\n+ tgen_andi(s, TCG_TYPE_I32, a0, a2);\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RR, NR, a0, a2);\n } else {\n- tcg_out_insn(s, RR, NR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, NRK, a0, a1, a2);\n }\n break;\n case INDEX_op_or_i32:\n+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];\n if (const_args[2]) {\n- tgen64_ori(s, args[0], args[2] & 0xffffffff);\n+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);\n+ tgen64_ori(s, a0, a2);\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RR, OR, a0, a2);\n } else {\n- tcg_out_insn(s, RR, OR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, ORK, a0, a1, a2);\n }\n break;\n case INDEX_op_xor_i32:\n+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];\n if (const_args[2]) {\n- tgen64_xori(s, args[0], args[2] & 0xffffffff);\n- } else {\n+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);\n+ tgen64_xori(s, a0, a2);\n+ } else if (a0 == a1) {\n tcg_out_insn(s, RR, XR, args[0], args[2]);\n+ } else {\n+ tcg_out_insn(s, RRF, XRK, a0, a1, a2);\n }\n break;\n \n@@ -1804,18 +1838,31 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n \n case INDEX_op_shl_i32:\n op = RS_SLL;\n+ op2 = RSY_SLLK;\n do_shift32:\n- if (const_args[2]) {\n- tcg_out_sh32(s, op, args[0], TCG_REG_NONE, args[2]);\n+ a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];\n+ if (a0 == a1) {\n+ if (const_args[2]) {\n+ tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2);\n+ } else {\n+ tcg_out_sh32(s, op, a0, a2, 0);\n+ }\n } else {\n- tcg_out_sh32(s, op, args[0], args[2], 0);\n+ /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */\n+ if (const_args[2]) {\n+ tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2);\n+ } else {\n+ tcg_out_sh64(s, op2, a0, a1, a2, 0);\n+ }\n }\n break;\n case INDEX_op_shr_i32:\n op = RS_SRL;\n+ op2 = RSY_SRLK;\n goto do_shift32;\n case INDEX_op_sar_i32:\n op = RS_SRA;\n+ op2 = RSY_SRAK;\n goto do_shift32;\n \n case INDEX_op_rotl_i32:\n@@ -1957,30 +2004,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n if (const_args[2]) {\n a2 = -a2;\n goto do_addi_64;\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RRE, SGR, a0, a2);\n } else {\n- tcg_out_insn(s, RRE, SGR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, SGRK, a0, a1, a2);\n }\n break;\n \n case INDEX_op_and_i64:\n+ a0 = args[0], a1 = args[1], a2 = args[2];\n if (const_args[2]) {\n+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);\n tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);\n- } else {\n+ } else if (a0 == a1) {\n tcg_out_insn(s, RRE, NGR, args[0], args[2]);\n+ } else {\n+ tcg_out_insn(s, RRF, NGRK, a0, a1, a2);\n }\n break;\n case INDEX_op_or_i64:\n+ a0 = args[0], a1 = args[1], a2 = args[2];\n if (const_args[2]) {\n- tgen64_ori(s, args[0], args[2]);\n+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);\n+ tgen64_ori(s, a0, a2);\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RRE, OGR, a0, a2);\n } else {\n- tcg_out_insn(s, RRE, OGR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, OGRK, a0, a1, a2);\n }\n break;\n case INDEX_op_xor_i64:\n+ a0 = args[0], a1 = args[1], a2 = args[2];\n if (const_args[2]) {\n- tgen64_xori(s, args[0], args[2]);\n+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);\n+ tgen64_xori(s, a0, a2);\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RRE, XGR, a0, a2);\n } else {\n- tcg_out_insn(s, RRE, XGR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, XGRK, a0, a1, a2);\n }\n break;\n \n@@ -2168,6 +2229,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_rC = { .args_ct_str = { \"r\", \"rC\" } };\n static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n+ static const TCGTargetOpDef r_r_rM = { .args_ct_str = { \"r\", \"r\", \"rM\" } };\n static const TCGTargetOpDef r_0_r = { .args_ct_str = { \"r\", \"0\", \"r\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n@@ -2211,7 +2273,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n return &r_r_ri;\n case INDEX_op_sub_i32:\n case INDEX_op_sub_i64:\n- return &r_0_ri;\n+ return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);\n \n case INDEX_op_mul_i32:\n /* If we have the general-instruction-extensions, then we have\n@@ -2227,32 +2289,32 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n OI[LH][LH] instructions. By rejecting certain negative ranges,\n the immediate load plus the reg-reg OR is smaller. */\n return (s390_facilities & FACILITY_EXT_IMM\n- ? &r_0_ri\n+ ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)\n : &r_0_rN);\n case INDEX_op_or_i64:\n return (s390_facilities & FACILITY_EXT_IMM\n- ? &r_0_rM\n+ ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)\n : &r_0_rN);\n \n case INDEX_op_xor_i32:\n /* Without EXT_IMM, no immediates are supported. Otherwise,\n rejecting certain negative ranges leads to smaller code. */\n return (s390_facilities & FACILITY_EXT_IMM\n- ? &r_0_ri\n+ ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)\n : &r_0_r);\n case INDEX_op_xor_i64:\n return (s390_facilities & FACILITY_EXT_IMM\n- ? &r_0_rM\n+ ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)\n : &r_0_r);\n \n case INDEX_op_and_i32:\n case INDEX_op_and_i64:\n- return &r_0_ri;\n+ return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);\n \n case INDEX_op_shl_i32:\n case INDEX_op_shr_i32:\n case INDEX_op_sar_i32:\n- return &r_0_ri;\n+ return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);\n \n case INDEX_op_shl_i64:\n case INDEX_op_shr_i64:\n","prefixes":["PULL","12/14"]}