{"id":810656,"url":"http://patchwork.ozlabs.org/api/patches/810656/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-10-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906144940.30880-10-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T14:49:35","name":"[PULL,09/14] tcg/s390: Merge muli facilities check to tcg_target_op_def","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ae756a145016ba1421b06d026eaaefa5e4e3715c","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-10-richard.henderson@linaro.org/mbox/","series":[{"id":1829,"url":"http://patchwork.ozlabs.org/api/series/1829/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1829","date":"2017-09-06T14:49:28","name":"[PULL,01/14] tcg: Remove support for ia64 as host","version":1,"mbox":"http://patchwork.ozlabs.org/series/1829/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810656/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810656/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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If we have the\n- general-instruction-extensions, then we have MULTIPLY SINGLE\n- IMMEDIATE with a signed 32-bit, otherwise we have only\n- MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */\n- if (s390_facilities & FACILITY_GEN_INST_EXT) {\n- return val == (int32_t)val;\n- } else {\n- return val == (int16_t)val;\n- }\n+ if (ct & TCG_CT_CONST_S16) {\n+ return val == (int16_t)val;\n+ } else if (ct & TCG_CT_CONST_S32) {\n+ return val == (int32_t)val;\n } else if (ct & TCG_CT_CONST_ADLI) {\n return tcg_match_add2i(type, val);\n } else if (ct & TCG_CT_CONST_ORI) {\n@@ -2239,7 +2237,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n- static const TCGTargetOpDef r_0_rK = { .args_ct_str = { \"r\", \"0\", \"rK\" } };\n+ static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n+ static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { \"r\", \"0\", \"rJ\" } };\n static const TCGTargetOpDef r_0_rO = { .args_ct_str = { \"r\", \"0\", \"rO\" } };\n static const TCGTargetOpDef r_0_rX = { .args_ct_str = { \"r\", \"0\", \"rX\" } };\n \n@@ -2274,9 +2273,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_sub_i32:\n case INDEX_op_sub_i64:\n return &r_0_ri;\n+\n case INDEX_op_mul_i32:\n+ /* If we have the general-instruction-extensions, then we have\n+ MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we\n+ have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */\n+ return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);\n case INDEX_op_mul_i64:\n- return &r_0_rK;\n+ return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);\n+\n case INDEX_op_or_i32:\n case INDEX_op_or_i64:\n return &r_0_rO;\n","prefixes":["PULL","09/14"]}