{"id":810653,"url":"http://patchwork.ozlabs.org/api/patches/810653/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-9-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906144940.30880-9-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T14:49:34","name":"[PULL,08/14] tcg/s390: Merge cmpi facilities check to tcg_target_op_def","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"037291e7179e0c15cfca05eba2be1e95e1c6004e","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-9-richard.henderson@linaro.org/mbox/","series":[{"id":1829,"url":"http://patchwork.ozlabs.org/api/series/1829/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1829","date":"2017-09-06T14:49:28","name":"[PULL,01/14] tcg: Remove support for ia64 as host","version":1,"mbox":"http://patchwork.ozlabs.org/series/1829/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810653/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810653/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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We have no insight here into whether the comparison is\n+ signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit\n+ signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses\n+ a 32-bit unsigned immediate. If we were to use the (semi)\n+ obvious \"val == (int32_t)val\" we would be enabling unsigned\n+ comparisons vs very large numbers. The only solution is to\n+ take the intersection of the ranges. */\n+ /* ??? Another possible solution is to simply lie and allow all\n+ constants here and force the out-of-range values into a temp\n+ register in tgen_cmp when we have knowledge of the actual\n+ comparison code in use. */\n+ ct->ct |= TCG_CT_CONST_U31;\n break;\n case 'Z':\n ct->ct |= TCG_CT_CONST_ZERO;\n@@ -463,35 +474,6 @@ static int tcg_match_xori(TCGType type, tcg_target_long val)\n return 1;\n }\n \n-/* Imediates to be used with comparisons. */\n-\n-static int tcg_match_cmpi(TCGType type, tcg_target_long val)\n-{\n- if (s390_facilities & FACILITY_EXT_IMM) {\n- /* The COMPARE IMMEDIATE instruction is available. */\n- if (type == TCG_TYPE_I32) {\n- /* We have a 32-bit immediate and can compare against anything. */\n- return 1;\n- } else {\n- /* ??? We have no insight here into whether the comparison is\n- signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit\n- signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses\n- a 32-bit unsigned immediate. If we were to use the (semi)\n- obvious \"val == (int32_t)val\" we would be enabling unsigned\n- comparisons vs very large numbers. The only solution is to\n- take the intersection of the ranges. */\n- /* ??? Another possible solution is to simply lie and allow all\n- constants here and force the out-of-range values into a temp\n- register in tgen_cmp when we have knowledge of the actual\n- comparison code in use. */\n- return val >= 0 && val <= 0x7fffffff;\n- }\n- } else {\n- /* Only the LOAD AND TEST instruction is available. */\n- return val == 0;\n- }\n-}\n-\n /* Immediates to be used with add2/sub2. */\n \n static int tcg_match_add2i(TCGType type, tcg_target_long val)\n@@ -537,8 +519,8 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,\n return tcg_match_ori(type, val);\n } else if (ct & TCG_CT_CONST_XORI) {\n return tcg_match_xori(type, val);\n- } else if (ct & TCG_CT_CONST_CMPI) {\n- return tcg_match_cmpi(type, val);\n+ } else if (ct & TCG_CT_CONST_U31) {\n+ return val >= 0 && val <= 0x7fffffff;\n } else if (ct & TCG_CT_CONST_ZERO) {\n return val == 0;\n }\n@@ -2252,7 +2234,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_r = { .args_ct_str = { \"r\", \"r\" } };\n static const TCGTargetOpDef r_L = { .args_ct_str = { \"r\", \"L\" } };\n static const TCGTargetOpDef L_L = { .args_ct_str = { \"L\", \"L\" } };\n+ static const TCGTargetOpDef r_ri = { .args_ct_str = { \"r\", \"ri\" } };\n static const TCGTargetOpDef r_rC = { .args_ct_str = { \"r\", \"rC\" } };\n+ static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rK = { .args_ct_str = { \"r\", \"0\", \"rK\" } };\n@@ -2320,8 +2304,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n return &r_r_ri;\n \n case INDEX_op_brcond_i32:\n+ /* Without EXT_IMM, only the LOAD AND TEST insn is available. */\n+ return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ);\n case INDEX_op_brcond_i64:\n- return &r_rC;\n+ return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ);\n \n case INDEX_op_bswap16_i32:\n case INDEX_op_bswap16_i64:\n@@ -2366,16 +2352,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_setcond_i32:\n case INDEX_op_setcond_i64:\n {\n- static const TCGTargetOpDef setc\n+ /* Without EXT_IMM, only the LOAD AND TEST insn is available. */\n+ static const TCGTargetOpDef setc_z\n+ = { .args_ct_str = { \"r\", \"r\", \"rZ\" } };\n+ static const TCGTargetOpDef setc_c\n = { .args_ct_str = { \"r\", \"r\", \"rC\" } };\n- return &setc;\n+ return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z);\n }\n case INDEX_op_movcond_i32:\n case INDEX_op_movcond_i64:\n {\n- static const TCGTargetOpDef movc\n+ /* Without EXT_IMM, only the LOAD AND TEST insn is available. */\n+ static const TCGTargetOpDef movc_z\n+ = { .args_ct_str = { \"r\", \"r\", \"rZ\", \"r\", \"0\" } };\n+ static const TCGTargetOpDef movc_c\n = { .args_ct_str = { \"r\", \"r\", \"rC\", \"r\", \"0\" } };\n- return &movc;\n+ return (s390_facilities & FACILITY_EXT_IMM ? &movc_c : &movc_z);\n }\n case INDEX_op_div2_i32:\n case INDEX_op_div2_i64:\n","prefixes":["PULL","08/14"]}