{"id":810651,"url":"http://patchwork.ozlabs.org/api/patches/810651/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-12-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906144940.30880-12-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T14:49:37","name":"[PULL,11/14] tcg/s390: Merge ori+xori facilities check to tcg_target_op_def","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0e48d1c51170b62afe66921b27f1e6a636feda00","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-12-richard.henderson@linaro.org/mbox/","series":[{"id":1829,"url":"http://patchwork.ozlabs.org/api/series/1829/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1829","date":"2017-09-06T14:49:28","name":"[PULL,01/14] tcg: Remove support for ia64 as host","version":1,"mbox":"http://patchwork.ozlabs.org/series/1829/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810651/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810651/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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We have no insight here into whether the comparison is\n@@ -424,60 +424,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n return ct_str;\n }\n \n-/* Immediates to be used with logical OR. This is an optimization only,\n- since a full 64-bit immediate OR can always be performed with 4 sequential\n- OI[LH][LH] instructions. What we're looking for is immediates that we\n- can load efficiently, and the immediate load plus the reg-reg OR is\n- smaller than the sequential OI's. */\n-\n-static int tcg_match_ori(TCGType type, tcg_target_long val)\n-{\n- if (s390_facilities & FACILITY_EXT_IMM) {\n- if (type == TCG_TYPE_I32) {\n- /* All 32-bit ORs can be performed with 1 48-bit insn. */\n- return 1;\n- }\n- }\n-\n- /* Look for negative values. These are best to load with LGHI. */\n- if (val < 0) {\n- if (val == (int16_t)val) {\n- return 0;\n- }\n- if (s390_facilities & FACILITY_EXT_IMM) {\n- if (val == (int32_t)val) {\n- return 0;\n- }\n- }\n- }\n-\n- return 1;\n-}\n-\n-/* Immediates to be used with logical XOR. This is almost, but not quite,\n- only an optimization. XOR with immediate is only supported with the\n- extended-immediate facility. That said, there are a few patterns for\n- which it is better to load the value into a register first. */\n-\n-static int tcg_match_xori(TCGType type, tcg_target_long val)\n-{\n- if ((s390_facilities & FACILITY_EXT_IMM) == 0) {\n- return 0;\n- }\n-\n- if (type == TCG_TYPE_I32) {\n- /* All 32-bit XORs can be performed with 1 48-bit insn. */\n- return 1;\n- }\n-\n- /* Look for negative values. These are best to load with LGHI. */\n- if (val < 0 && val == (int32_t)val) {\n- return 0;\n- }\n-\n- return 1;\n-}\n-\n /* Test if a constant matches the constraint. */\n static int tcg_target_const_match(tcg_target_long val, TCGType type,\n const TCGArgConstraint *arg_ct)\n@@ -499,10 +445,10 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,\n return val == (int32_t)val;\n } else if (ct & TCG_CT_CONST_S33) {\n return val >= -0xffffffffll && val <= 0xffffffffll;\n- } else if (ct & TCG_CT_CONST_ORI) {\n- return tcg_match_ori(type, val);\n- } else if (ct & TCG_CT_CONST_XORI) {\n- return tcg_match_xori(type, val);\n+ } else if (ct & TCG_CT_CONST_NN16) {\n+ return !(val < 0 && val == (int16_t)val);\n+ } else if (ct & TCG_CT_CONST_NN32) {\n+ return !(val < 0 && val == (int32_t)val);\n } else if (ct & TCG_CT_CONST_U31) {\n return val >= 0 && val <= 0x7fffffff;\n } else if (ct & TCG_CT_CONST_ZERO) {\n@@ -2222,11 +2168,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_rC = { .args_ct_str = { \"r\", \"rC\" } };\n static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n+ static const TCGTargetOpDef r_0_r = { .args_ct_str = { \"r\", \"0\", \"r\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { \"r\", \"0\", \"rJ\" } };\n- static const TCGTargetOpDef r_0_rO = { .args_ct_str = { \"r\", \"0\", \"rO\" } };\n- static const TCGTargetOpDef r_0_rX = { .args_ct_str = { \"r\", \"0\", \"rX\" } };\n+ static const TCGTargetOpDef r_0_rN = { .args_ct_str = { \"r\", \"0\", \"rN\" } };\n+ static const TCGTargetOpDef r_0_rM = { .args_ct_str = { \"r\", \"0\", \"rM\" } };\n static const TCGTargetOpDef a2_r\n = { .args_ct_str = { \"r\", \"r\", \"0\", \"1\", \"r\", \"r\" } };\n static const TCGTargetOpDef a2_ri\n@@ -2275,11 +2222,29 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);\n \n case INDEX_op_or_i32:\n+ /* The use of [iNM] constraints are optimization only, since a full\n+ 64-bit immediate OR can always be performed with 4 sequential\n+ OI[LH][LH] instructions. By rejecting certain negative ranges,\n+ the immediate load plus the reg-reg OR is smaller. */\n+ return (s390_facilities & FACILITY_EXT_IMM\n+ ? &r_0_ri\n+ : &r_0_rN);\n case INDEX_op_or_i64:\n- return &r_0_rO;\n+ return (s390_facilities & FACILITY_EXT_IMM\n+ ? &r_0_rM\n+ : &r_0_rN);\n+\n case INDEX_op_xor_i32:\n+ /* Without EXT_IMM, no immediates are supported. Otherwise,\n+ rejecting certain negative ranges leads to smaller code. */\n+ return (s390_facilities & FACILITY_EXT_IMM\n+ ? &r_0_ri\n+ : &r_0_r);\n case INDEX_op_xor_i64:\n- return &r_0_rX;\n+ return (s390_facilities & FACILITY_EXT_IMM\n+ ? &r_0_rM\n+ : &r_0_r);\n+\n case INDEX_op_and_i32:\n case INDEX_op_and_i64:\n return &r_0_ri;\n","prefixes":["PULL","11/14"]}