{"id":810642,"url":"http://patchwork.ozlabs.org/api/patches/810642/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906142658.58298-3-marcel@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906142658.58298-3-marcel@redhat.com>","list_archive_url":null,"date":"2017-09-06T14:26:58","name":"[2/2] hw/pcie: disable IO port fwd by default for pcie-root-port","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ea098fd2122aedfcbc85609471ba671c6a7b242e","submitter":{"id":65362,"url":"http://patchwork.ozlabs.org/api/people/65362/?format=json","name":"Marcel Apfelbaum","email":"marcel@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906142658.58298-3-marcel@redhat.com/mbox/","series":[{"id":1825,"url":"http://patchwork.ozlabs.org/api/series/1825/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1825","date":"2017-09-06T14:26:57","name":"hw/pcie: disable IO port fwd by default for pcie-root-port.","version":1,"mbox":"http://patchwork.ozlabs.org/series/1825/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810642/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810642/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=marcel@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnQxR4VjXz9t4t\n\tfor ;\n\tThu, 7 Sep 2017 00:31:07 +1000 (AEST)","from localhost ([::1]:36425 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpbM9-0002bj-OK\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 10:31:05 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:60301)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpbIi-0008T3-3C\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:27:33 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dpbIg-0004oc-SB\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:27:32 -0400","from mx1.redhat.com ([209.132.183.28]:51092)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1dpbIg-0004ng-JJ\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:27:30 -0400","from smtp.corp.redhat.com\n\t(int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id A578DC047B62;\n\tWed, 6 Sep 2017 14:27:29 +0000 (UTC)","from localhost.localdomain (unknown [10.35.206.58])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id D3C347DEFF;\n\tWed, 6 Sep 2017 14:27:18 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com A578DC047B62","From":"Marcel Apfelbaum ","To":"qemu-devel@nongnu.org","Date":"Wed, 6 Sep 2017 17:26:58 +0300","Message-Id":"<20170906142658.58298-3-marcel@redhat.com>","In-Reply-To":"<20170906142658.58298-1-marcel@redhat.com>","References":"<20170906142658.58298-1-marcel@redhat.com>","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.14","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.31]);\n\tWed, 06 Sep 2017 14:27:29 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"[Qemu-devel] [PATCH 2/2] hw/pcie: disable IO port fwd by default\n\tfor pcie-root-port","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"marcel@redhat.com, pbonzini@redhat.com, rth@twiddle.net,\n\tehabkost@redhat.com, mst@redhat.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"For most cases the devices attached to PCIe Root Ports\ndo not need IO ports range, add an 'enable-io-fwd' property\nmaking it false by default, but keeping it true for older machines.\n\nSigned-off-by: Marcel Apfelbaum \n---\n hw/pci-bridge/gen_pcie_root_port.c | 38 ++++++++++++++++++++++++++++++++++++++\n include/hw/compat.h | 6 +++++-\n 2 files changed, 43 insertions(+), 1 deletion(-)","diff":"diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c\nindex cb694d6da5..cbdeb73e2c 100644\n--- a/hw/pci-bridge/gen_pcie_root_port.c\n+++ b/hw/pci-bridge/gen_pcie_root_port.c\n@@ -20,12 +20,26 @@\n #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100\n #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1\n \n+#define GEN_PCIE_ROOT_PORT(obj) \\\n+ OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT)\n+#define GEN_PCIE_ROOT_PORT_CLASS(klass) \\\n+ OBJECT_CLASS_CHECK(GenPCIERootPortClass, (klass), TYPE_GEN_PCIE_ROOT_PORT)\n+#define GEN_PCIE_ROOT_PORT_GET_CLASS(obj) \\\n+ OBJECT_GET_CLASS(GenPCIERootPortClass, (obj), TYPE_GEN_PCIE_ROOT_PORT)\n+\n+typedef struct GenPCIERootPortClass {\n+ PCIERootPortClass parent_class;\n+\n+ DeviceRealize parent_realize;\n+} GenPCIERootPortClass;\n+\n typedef struct GenPCIERootPort {\n /*< private >*/\n PCIESlot parent_obj;\n /*< public >*/\n \n bool migrate_msix;\n+ bool enable_io_fwd;\n } GenPCIERootPort;\n \n static uint8_t gen_rp_aer_vector(const PCIDevice *d)\n@@ -60,6 +74,25 @@ static bool gen_rp_test_migrate_msix(void *opaque, int version_id)\n return rp->migrate_msix;\n }\n \n+static void gen_rp_realize(DeviceState *d, Error **errp)\n+{\n+ GenPCIERootPortClass *grpc = GEN_PCIE_ROOT_PORT_GET_CLASS(d);\n+ GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);\n+ PCIDevice *pci_dev = PCI_DEVICE(d);\n+\n+ grpc->parent_realize(DEVICE(d), errp);\n+ if (*errp) {\n+ return;\n+ }\n+\n+ if (!grp->enable_io_fwd) {\n+ pci_word_test_and_clear_mask(pci_dev->wmask + PCI_COMMAND,\n+ PCI_COMMAND_IO);\n+ pci_dev->wmask[PCI_IO_BASE] = 0;\n+ pci_dev->wmask[PCI_IO_LIMIT] = 0;\n+ }\n+}\n+\n static const VMStateDescription vmstate_rp_dev = {\n .name = \"pcie-root-port\",\n .version_id = 1,\n@@ -78,6 +111,7 @@ static const VMStateDescription vmstate_rp_dev = {\n \n static Property gen_rp_props[] = {\n DEFINE_PROP_BOOL(\"x-migrate-msix\", GenPCIERootPort, migrate_msix, true),\n+ DEFINE_PROP_BOOL(\"enable-io-fwd\", GenPCIERootPort, enable_io_fwd, false),\n DEFINE_PROP_END_OF_LIST()\n };\n \n@@ -86,6 +120,7 @@ static void gen_rp_dev_class_init(ObjectClass *klass, void *data)\n DeviceClass *dc = DEVICE_CLASS(klass);\n PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);\n PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);\n+ GenPCIERootPortClass *grpc = GEN_PCIE_ROOT_PORT_CLASS(klass);\n \n k->vendor_id = PCI_VENDOR_ID_REDHAT;\n k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;\n@@ -96,6 +131,8 @@ static void gen_rp_dev_class_init(ObjectClass *klass, void *data)\n rpc->interrupts_init = gen_rp_interrupts_init;\n rpc->interrupts_uninit = gen_rp_interrupts_uninit;\n rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;\n+ grpc->parent_realize = dc->realize;\n+ dc->realize = gen_rp_realize;\n }\n \n static const TypeInfo gen_rp_dev_info = {\n@@ -103,6 +140,7 @@ static const TypeInfo gen_rp_dev_info = {\n .parent = TYPE_PCIE_ROOT_PORT,\n .instance_size = sizeof(GenPCIERootPort),\n .class_init = gen_rp_dev_class_init,\n+ .class_size = sizeof(GenPCIERootPortClass),\n };\n \n static void gen_rp_register_types(void)\ndiff --git a/include/hw/compat.h b/include/hw/compat.h\nindex 3e101f8f67..843bf4a3a5 100644\n--- a/include/hw/compat.h\n+++ b/include/hw/compat.h\n@@ -2,7 +2,11 @@\n #define HW_COMPAT_H\n \n #define HW_COMPAT_2_10 \\\n- /* empty */\n+ {\\\n+ .driver = \"pcie-root-port\",\\\n+ .property = \"enable-io-fwd\",\\\n+ .value = \"true\",\\\n+ },\n \n #define HW_COMPAT_2_9 \\\n {\\\n","prefixes":["2/2"]}