{"id":810477,"url":"http://patchwork.ozlabs.org/api/patches/810477/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170906094755.22262-4-wenyou.yang@microchip.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906094755.22262-4-wenyou.yang@microchip.com>","list_archive_url":null,"date":"2017-09-06T09:47:53","name":"[U-Boot,v2,3/5] ARM: at91: Remove hardware.h included in configs","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"a4363d521f5c50dacc7bc1bacc7adf2bbf9d2951","submitter":{"id":69532,"url":"http://patchwork.ozlabs.org/api/people/69532/?format=json","name":"Wenyou Yang","email":"Wenyou.Yang@microchip.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170906094755.22262-4-wenyou.yang@microchip.com/mbox/","series":[{"id":1742,"url":"http://patchwork.ozlabs.org/api/series/1742/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=1742","date":"2017-09-06T09:47:50","name":"configs: at91: Remove value of CONFIG_SYS_EXTRA_OPTIONS option","version":2,"mbox":"http://patchwork.ozlabs.org/series/1742/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810477/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810477/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnJlC0cn3z9sCZ\n\tfor ;\n\tWed, 6 Sep 2017 19:51:51 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid AAB44C21F12; Wed, 6 Sep 2017 09:50:10 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 36245C21EE4;\n\tWed, 6 Sep 2017 09:49:55 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 8E19EC21EEA; Wed, 6 Sep 2017 09:49:23 +0000 (UTC)","from eusmtp01.atmel.com (eusmtp01.atmel.com [212.144.249.243])\n\tby lists.denx.de (Postfix) with ESMTPS id 2ABD5C21E18\n\tfor ; Wed, 6 Sep 2017 09:49:19 +0000 (UTC)","from apsmtp01.atmel.com (10.168.254.31) by eusmtp01.atmel.com\n\t(10.145.145.31) with Microsoft SMTP Server id 14.3.235.1;\n\tWed, 6 Sep 2017 11:48:37 +0200","from shaarm01.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com\n\t(10.168.254.31) with Microsoft SMTP Server id 14.3.235.1;\n\tWed, 6 Sep 2017 17:52:55 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","From":"Wenyou Yang ","To":"U-Boot Mailing List , Simon Glass\n\t, Heiko Schocher , Tom Rini\n\t, Andreas ","Date":"Wed, 6 Sep 2017 17:47:53 +0800","Message-ID":"<20170906094755.22262-4-wenyou.yang@microchip.com>","X-Mailer":"git-send-email 2.13.0","In-Reply-To":"<20170906094755.22262-1-wenyou.yang@microchip.com>","References":"<20170906094755.22262-1-wenyou.yang@microchip.com>","MIME-Version":"1.0","Subject":"[U-Boot] [PATCH v2 3/5] ARM: at91: Remove hardware.h included in\n\tconfigs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Wenyou Yang \n\nAs said in READRE.kconfig, include/configs/*.h will be removed\nafter all options are switched to Kconfig. As the first step,\nremove the follow line from include/configs/*.h.\n\n #include \n\nSigned-off-by: Wenyou Yang \n---\n\nChanges in v2: None\n\n arch/arm/mach-at91/atmel_sfr.c | 1 +\n arch/arm/mach-at91/matrix.c | 1 +\n arch/arm/mach-at91/phy.c | 1 +\n drivers/pinctrl/pinctrl-at91.c | 1 +\n include/configs/at91-sama5_common.h | 2 --\n include/configs/at91sam9m10g45ek.h | 4 +---\n include/configs/at91sam9n12ek.h | 8 +-------\n include/configs/at91sam9x5ek.h | 2 --\n include/configs/ma5d4evk.h | 9 ++++++---\n include/configs/sama5d2_ptc.h | 10 ++++++----\n include/configs/sama5d2_xplained.h | 2 +-\n include/configs/sama5d3_xplained.h | 10 +++++-----\n include/configs/sama5d3xek.h | 8 ++++----\n include/configs/sama5d4_xplained.h | 4 ++--\n include/configs/sama5d4ek.h | 4 ++--\n include/configs/vinco.h | 11 +++++++----\n 16 files changed, 39 insertions(+), 39 deletions(-)","diff":"diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c\nindex adf44c6a94..d595ba8836 100644\n--- a/arch/arm/mach-at91/atmel_sfr.c\n+++ b/arch/arm/mach-at91/atmel_sfr.c\n@@ -6,6 +6,7 @@\n */\n \n #include \n+#include \n #include \n #include \n \ndiff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c\nindex 57d72700d3..08659c87d4 100644\n--- a/arch/arm/mach-at91/matrix.c\n+++ b/arch/arm/mach-at91/matrix.c\n@@ -6,6 +6,7 @@\n */\n \n #include \n+#include \n #include \n #include \n \ndiff --git a/arch/arm/mach-at91/phy.c b/arch/arm/mach-at91/phy.c\nindex ddd70f5ff0..adb761e1ac 100644\n--- a/arch/arm/mach-at91/phy.c\n+++ b/arch/arm/mach-at91/phy.c\n@@ -13,6 +13,7 @@\n */\n \n #include \n+#include \n #include \n #include \n #include \ndiff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c\nindex 38c435e37a..81f30eabe9 100644\n--- a/drivers/pinctrl/pinctrl-at91.c\n+++ b/drivers/pinctrl/pinctrl-at91.c\n@@ -10,6 +10,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \ndiff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h\nindex ff17b4eb4b..435c7dfa8e 100644\n--- a/include/configs/at91-sama5_common.h\n+++ b/include/configs/at91-sama5_common.h\n@@ -10,8 +10,6 @@\n #ifndef __AT91_SAMA5_COMMON_H\n #define __AT91_SAMA5_COMMON_H\n \n-#include \n-\n #define CONFIG_SYS_TEXT_BASE\t\t0x26f00000\n \n /* ARM asynchronous clock */\ndiff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h\nindex 22db94772d..36acaa5506 100644\n--- a/include/configs/at91sam9m10g45ek.h\n+++ b/include/configs/at91sam9m10g45ek.h\n@@ -11,8 +11,6 @@\n #ifndef __CONFIG_H\n #define __CONFIG_H\n \n-#include \n-\n #define CONFIG_SYS_TEXT_BASE\t\t0x73f00000\n \n #define CONFIG_ATMEL_LEGACY\t\t/* required until (g)pio is fixed */\n@@ -52,7 +50,7 @@\n \n /* SDRAM */\n #define CONFIG_NR_DRAM_BANKS\t\t1\n-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6\n+#define CONFIG_SYS_SDRAM_BASE 0x70000000\n #define CONFIG_SYS_SDRAM_SIZE\t\t0x08000000\n \n #define CONFIG_SYS_INIT_SP_ADDR \\\ndiff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h\nindex 7d70d8892a..c9adcf9754 100644\n--- a/include/configs/at91sam9n12ek.h\n+++ b/include/configs/at91sam9n12ek.h\n@@ -10,12 +10,6 @@\n #ifndef __AT91SAM9N12_CONFIG_H_\n #define __AT91SAM9N12_CONFIG_H_\n \n-/*\n- * SoC must be defined first, before hardware.h is included.\n- * In this case SoC is defined in boards.cfg.\n- */\n-#include \n-\n #define CONFIG_SYS_TEXT_BASE\t\t0x26f00000\n \n /* ARM asynchronous clock */\n@@ -55,7 +49,7 @@\n * that address while providing maximum stack area below.\n */\n # define CONFIG_SYS_INIT_SP_ADDR \\\n-\t(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)\n+\t(0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)\n \n /* DataFlash */\n #ifdef CONFIG_CMD_SF\ndiff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h\nindex c50e0b816f..eb798442ca 100644\n--- a/include/configs/at91sam9x5ek.h\n+++ b/include/configs/at91sam9x5ek.h\n@@ -9,8 +9,6 @@\n #ifndef __CONFIG_H__\n #define __CONFIG_H__\n \n-#include \n-\n #define CONFIG_SYS_TEXT_BASE\t\t0x26f00000\n \n /* ARM asynchronous clock */\ndiff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h\nindex 50b21c9d97..0fe1bc1c1d 100644\n--- a/include/configs/ma5d4evk.h\n+++ b/include/configs/ma5d4evk.h\n@@ -14,11 +14,14 @@\n #define CONFIG_SYS_USE_SERIALFLASH\t1\n #define CONFIG_BOARD_LATE_INIT\n \n+/* Timer */\n+#define CONFIG_SYS_TIMER_COUNTER\t0xfc06863c\n+\n /*\n * Memory configurations\n */\n #define CONFIG_NR_DRAM_BANKS\t\t1\n-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x20000000\n #define CONFIG_SYS_SDRAM_SIZE\t\t0x10000000\n \n #ifdef CONFIG_SPL_BUILD\n@@ -45,8 +48,8 @@\n * Serial Driver\n */\n #define CONFIG_ATMEL_USART\n-#define CONFIG_USART_BASE\t\tATMEL_BASE_USART0\n-#define CONFIG_USART_ID\t\t\tATMEL_ID_USART0\n+#define CONFIG_USART_BASE\t\t0xf802c000\n+#define CONFIG_USART_ID\t\t\t6\n \n /*\n * Ethernet\ndiff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h\nindex b04781893d..75a81f1473 100644\n--- a/include/configs/sama5d2_ptc.h\n+++ b/include/configs/sama5d2_ptc.h\n@@ -14,12 +14,14 @@\n \n /* serial console */\n #define CONFIG_ATMEL_USART\n-#define CONFIG_USART_BASE\t\tATMEL_BASE_UART0\n-#define CONFIG_USART_ID\t\t\tATMEL_ID_UART0\n+#define CONFIG_USART_BASE\t\t0xf801c000\n+#define CONFIG_USART_ID\t\t\t24\n \n-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x20000000\n #define CONFIG_SYS_SDRAM_SIZE\t\t0x20000000\n \n+#define CONFIG_SYS_TIMER_COUNTER\t0xf804803c\n+\n #ifdef CONFIG_SPL_BUILD\n #define CONFIG_SYS_INIT_SP_ADDR\t\t0x210000\n #else\n@@ -48,7 +50,7 @@\n #ifdef CONFIG_CMD_NAND\n #define CONFIG_NAND_ATMEL\n #define CONFIG_SYS_MAX_NAND_DEVICE\t1\n-#define CONFIG_SYS_NAND_BASE\t\tATMEL_BASE_CS3\n+#define CONFIG_SYS_NAND_BASE\t\t0x80000000\n /* our ALE is AD21 */\n #define CONFIG_SYS_NAND_MASK_ALE\t(1 << 21)\n /* our CLE is AD22 */\ndiff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h\nindex 9ceb91924d..2a9e9729d1 100644\n--- a/include/configs/sama5d2_xplained.h\n+++ b/include/configs/sama5d2_xplained.h\n@@ -16,7 +16,7 @@\n \n /* SDRAM */\n #define CONFIG_NR_DRAM_BANKS\t\t1\n-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS\n+#define CONFIG_SYS_SDRAM_BASE 0x20000000\n #define CONFIG_SYS_SDRAM_SIZE\t\t0x20000000\n \n #ifdef CONFIG_SPL_BUILD\ndiff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h\nindex 05600c81ff..54ea98d454 100644\n--- a/include/configs/sama5d3_xplained.h\n+++ b/include/configs/sama5d3_xplained.h\n@@ -16,16 +16,16 @@\n * This needs to be defined for the OHCI code to work but it is defined as\n * ATMEL_ID_UHPHS in the CPU specific header files.\n */\n-#define ATMEL_ID_UHP\t\t\tATMEL_ID_UHPHS\n+#define ATMEL_ID_UHP\t\t\t32\n \n /*\n * Specify the clock enable bit in the PMC_SCER register.\n */\n-#define ATMEL_PMC_UHP\t\t\tAT91SAM926x_PMC_UHP\n+#define ATMEL_PMC_UHP\t\t\t(1 << 6)\n \n /* SDRAM */\n #define CONFIG_NR_DRAM_BANKS\t\t1\n-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS\n+#define CONFIG_SYS_SDRAM_BASE 0x20000000\n #define CONFIG_SYS_SDRAM_SIZE\t\t0x10000000\n \n #ifdef CONFIG_SPL_BUILD\n@@ -39,7 +39,7 @@\n #ifdef CONFIG_CMD_NAND\n #define CONFIG_NAND_ATMEL\n #define CONFIG_SYS_MAX_NAND_DEVICE\t1\n-#define CONFIG_SYS_NAND_BASE\t\tATMEL_BASE_CS3\n+#define CONFIG_SYS_NAND_BASE\t\t0x60000000\n /* our ALE is AD21 */\n #define CONFIG_SYS_NAND_MASK_ALE\t(1 << 21)\n /* our CLE is AD22 */\n@@ -62,7 +62,7 @@\n #define CONFIG_USB_ATMEL_CLK_SEL_UPLL\n #define CONFIG_USB_OHCI_NEW\n #define CONFIG_SYS_USB_OHCI_CPU_INIT\n-#define CONFIG_SYS_USB_OHCI_REGS_BASE\t\tATMEL_BASE_OHCI\n+#define CONFIG_SYS_USB_OHCI_REGS_BASE\t\t0x00600000\n #define CONFIG_SYS_USB_OHCI_SLOT_NAME\t\t\"SAMA5D3 Xplained\"\n #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS\t2\n #endif\ndiff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h\nindex 29b7e8b50a..a7223e2cf0 100644\n--- a/include/configs/sama5d3xek.h\n+++ b/include/configs/sama5d3xek.h\n@@ -21,12 +21,12 @@\n * This needs to be defined for the OHCI code to work but it is defined as\n * ATMEL_ID_UHPHS in the CPU specific header files.\n */\n-#define ATMEL_ID_UHP\t\t\tATMEL_ID_UHPHS\n+#define ATMEL_ID_UHP\t\t\t32\n \n /*\n * Specify the clock enable bit in the PMC_SCER register.\n */\n-#define ATMEL_PMC_UHP\t\t\tAT91SAM926x_PMC_UHP\n+#define ATMEL_PMC_UHP\t\t\t(1 << 6)\n \n /* LCD */\n #define LCD_BPP\t\t\t\tLCD_COLOR16\n@@ -52,7 +52,7 @@\n \n /* SDRAM */\n #define CONFIG_NR_DRAM_BANKS\t\t1\n-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS\n+#define CONFIG_SYS_SDRAM_BASE 0x20000000\n #define CONFIG_SYS_SDRAM_SIZE\t\t0x20000000\n \n #ifdef CONFIG_SPL_BUILD\n@@ -72,7 +72,7 @@\n #ifdef CONFIG_CMD_NAND\n #define CONFIG_NAND_ATMEL\n #define CONFIG_SYS_MAX_NAND_DEVICE\t1\n-#define CONFIG_SYS_NAND_BASE\t\tATMEL_BASE_CS3\n+#define CONFIG_SYS_NAND_BASE\t\t0x60000000\n /* our ALE is AD21 */\n #define CONFIG_SYS_NAND_MASK_ALE\t(1 << 21)\n /* our CLE is AD22 */\ndiff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h\nindex c8462b0b64..9f0f96f799 100644\n--- a/include/configs/sama5d4_xplained.h\n+++ b/include/configs/sama5d4_xplained.h\n@@ -14,7 +14,7 @@\n \n /* SDRAM */\n #define CONFIG_NR_DRAM_BANKS\t\t1\n-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS\n+#define CONFIG_SYS_SDRAM_BASE 0x20000000\n #define CONFIG_SYS_SDRAM_SIZE\t\t0x20000000\n \n #ifdef CONFIG_SPL_BUILD\n@@ -34,7 +34,7 @@\n #ifdef CONFIG_CMD_NAND\n #define CONFIG_NAND_ATMEL\n #define CONFIG_SYS_MAX_NAND_DEVICE\t1\n-#define CONFIG_SYS_NAND_BASE\t\tATMEL_BASE_CS3\n+#define CONFIG_SYS_NAND_BASE\t\t0x80000000\n /* our ALE is AD21 */\n #define CONFIG_SYS_NAND_MASK_ALE\t(1 << 21)\n /* our CLE is AD22 */\ndiff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h\nindex fc16ed0420..0410d65ea0 100644\n--- a/include/configs/sama5d4ek.h\n+++ b/include/configs/sama5d4ek.h\n@@ -14,7 +14,7 @@\n \n /* SDRAM */\n #define CONFIG_NR_DRAM_BANKS\t\t1\n-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS\n+#define CONFIG_SYS_SDRAM_BASE 0x20000000\n #define CONFIG_SYS_SDRAM_SIZE\t\t0x20000000\n \n #ifdef CONFIG_SPL_BUILD\n@@ -34,7 +34,7 @@\n #ifdef CONFIG_CMD_NAND\n #define CONFIG_NAND_ATMEL\n #define CONFIG_SYS_MAX_NAND_DEVICE\t1\n-#define CONFIG_SYS_NAND_BASE\t\tATMEL_BASE_CS3\n+#define CONFIG_SYS_NAND_BASE\t\t0x80000000\n /* our ALE is AD21 */\n #define CONFIG_SYS_NAND_MASK_ALE\t(1 << 21)\n /* our CLE is AD22 */\ndiff --git a/include/configs/vinco.h b/include/configs/vinco.h\nindex e4020d00ce..8c45f4a32e 100644\n--- a/include/configs/vinco.h\n+++ b/include/configs/vinco.h\n@@ -23,12 +23,15 @@\n \n /* serial console */\n #define CONFIG_ATMEL_USART\n-#define CONFIG_USART_BASE\t\tATMEL_BASE_USART3\n-#define\tCONFIG_USART_ID\t\t\tATMEL_ID_USART3\n+#define CONFIG_USART_BASE\t\t0xfc00c000\n+#define CONFIG_USART_ID\t\t\t30\n+\n+/* Timer */\n+#define CONFIG_SYS_TIMER_COUNTER\t0xfc06863c\n \n /* SDRAM */\n #define CONFIG_NR_DRAM_BANKS\t\t1\n-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS\n+#define CONFIG_SYS_SDRAM_BASE 0x20000000\n #define CONFIG_SYS_SDRAM_SIZE\t\t0x4000000\n \n #define CONFIG_SYS_INIT_SP_ADDR \\\n@@ -55,7 +58,7 @@\n #ifdef CONFIG_CMD_MMC\n #define CONFIG_SUPPORT_EMMC_BOOT\n #define CONFIG_GENERIC_ATMEL_MCI\n-#define ATMEL_BASE_MMCI\t\t\tATMEL_BASE_MCI1\n+#define ATMEL_BASE_MMCI\t\t\t0xfc000000\n #define CONFIG_SYS_MMC_CLK_OD\t\t500000\n \n /* For generating MMC partitions */\n","prefixes":["U-Boot","v2","3/5"]}