{"id":810438,"url":"http://patchwork.ozlabs.org/api/patches/810438/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906082748.28520-1-nikunj@linux.vnet.ibm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906082748.28520-1-nikunj@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-09-06T08:27:48","name":"ppc/pnv: fix cores per chip for multiple cpus","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"763f953fb552d9327760566075e423bab2eba8d4","submitter":{"id":17189,"url":"http://patchwork.ozlabs.org/api/people/17189/?format=json","name":"Nikunj A Dadhania","email":"nikunj@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906082748.28520-1-nikunj@linux.vnet.ibm.com/mbox/","series":[{"id":1718,"url":"http://patchwork.ozlabs.org/api/series/1718/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1718","date":"2017-09-06T08:27:48","name":"ppc/pnv: fix cores per chip for multiple cpus","version":1,"mbox":"http://patchwork.ozlabs.org/series/1718/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810438/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810438/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnGwr6Y8pz9s2G\n\tfor ;\n\tWed, 6 Sep 2017 18:30:04 +1000 (AEST)","from localhost ([::1]:34946 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dpVik-0000OZ-Rx\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 04:30:02 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:48375)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dpViD-0000MV-2k\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 04:29:29 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dpVi8-0003NZ-W0\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 04:29:29 -0400","from mx0a-001b2d01.pphosted.com ([148.163.156.1]:36367)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dpVi8-0003NE-Na\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 04:29:24 -0400","from pps.filterd (m0098393.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv868TG7K143724\n\tfor ; Wed, 6 Sep 2017 04:29:23 -0400","from e23smtp06.au.ibm.com (e23smtp06.au.ibm.com [202.81.31.148])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2ct76an5wu-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Wed, 06 Sep 2017 04:29:22 -0400","from localhost\n\tby e23smtp06.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tWed, 6 Sep 2017 18:29:18 +1000","from d23av05.au.ibm.com (d23av05.au.ibm.com [9.190.234.119])\n\tby d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tv868S2CL33226768; Wed, 6 Sep 2017 18:28:02 +1000","from d23av05.au.ibm.com (localhost [127.0.0.1])\n\tby d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tv868S2dh028128; Wed, 6 Sep 2017 18:28:02 +1000","from abhimanyu.in.ibm.com (abhimanyu.in.ibm.com [9.124.35.100])\n\tby d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tv868Rw9o028060; Wed, 6 Sep 2017 18:27:59 +1000"],"From":"Nikunj A Dadhania ","To":"qemu-ppc@nongnu.org, david@gibson.dropbear.id.au","Date":"Wed, 6 Sep 2017 13:57:48 +0530","X-Mailer":"git-send-email 2.9.3","X-TM-AS-MML":"disable","x-cbid":"17090608-0040-0000-0000-000003534340","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17090608-0041-0000-0000-00000CD1593D","Message-Id":"<20170906082748.28520-1-nikunj@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-06_02:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709060117","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy]","X-Received-From":"148.163.156.1","Subject":"[Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org,\n\tNikunj A Dadhania , clg@kaod.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"When the user does not provide the cpu topology, e.g. \"-smp 4\", machine fails to\ninitialize 4 cpus. Compute the chip per cores depending on the number of chips\nand smt threads.\n\nSigned-off-by: Nikunj A Dadhania \n---\n hw/ppc/pnv.c | 20 ++++++++++++++++++--\n 1 file changed, 18 insertions(+), 2 deletions(-)","diff":"diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c\nindex 9724719..3fbaafb 100644\n--- a/hw/ppc/pnv.c\n+++ b/hw/ppc/pnv.c\n@@ -642,7 +642,7 @@ static void ppc_powernv_init(MachineState *machine)\n MemoryRegion *ram;\n char *fw_filename;\n long fw_size;\n- int i;\n+ int i, cores_per_chip;\n char *chip_typename;\n PCIBus *pbus;\n bool has_gfx = false;\n@@ -710,6 +710,22 @@ static void ppc_powernv_init(MachineState *machine)\n }\n \n pnv->chips = g_new0(PnvChip *, pnv->num_chips);\n+\n+ /* If user has specified number of cores, use it. Otherwise, compute it. */\n+ if (smp_cores != 1) {\n+ cores_per_chip = smp_cores;\n+ } else {\n+ cores_per_chip = smp_cpus / (smp_threads * pnv->num_chips);\n+ }\n+\n+ if (smp_cpus != (smp_threads * pnv->num_chips * cores_per_chip)) {\n+ error_report(\"cpu topology not balanced: \"\n+ \"chips (%u) * cores (%u) * threads (%u) != \"\n+ \"number of cpus (%u)\",\n+ pnv->num_chips, cores_per_chip, smp_threads, smp_cpus);\n+ exit(1);\n+ }\n+\n for (i = 0; i < pnv->num_chips; i++) {\n char chip_name[32];\n Object *chip = object_new(chip_typename);\n@@ -728,7 +744,7 @@ static void ppc_powernv_init(MachineState *machine)\n object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);\n object_property_set_int(chip, PNV_CHIP_HWID(i), \"chip-id\",\n &error_fatal);\n- object_property_set_int(chip, smp_cores, \"nr-cores\", &error_fatal);\n+ object_property_set_int(chip, cores_per_chip, \"nr-cores\", &error_fatal);\n object_property_set_int(chip, 1, \"num-phbs\", &error_fatal);\n object_property_set_bool(chip, true, \"realized\", &error_fatal);\n }\n","prefixes":[]}