{"id":810249,"url":"http://patchwork.ozlabs.org/api/patches/810249/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170905182714.27030.75573.stgit@bhelgaas-glaptop.roam.corp.google.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170905182714.27030.75573.stgit@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-09-05T18:27:14","name":"[3/4] PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"eba7372030ce1b26cbbd65f972167fe95bf58c7f","submitter":{"id":7584,"url":"http://patchwork.ozlabs.org/api/people/7584/?format=json","name":"Bjorn Helgaas","email":"bhelgaas@google.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170905182714.27030.75573.stgit@bhelgaas-glaptop.roam.corp.google.com/mbox/","series":[{"id":1628,"url":"http://patchwork.ozlabs.org/api/series/1628/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=1628","date":"2017-09-05T18:26:52","name":"iproc/xgene PCIe cap & whitespace cleanup","version":1,"mbox":"http://patchwork.ozlabs.org/series/1628/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810249/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810249/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org; dmarc=fail (p=reject dis=none)\n\theader.from=google.com","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmwDQ10Hvz9sCZ\n\tfor ;\n\tWed, 6 Sep 2017 04:27:18 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752209AbdIES1R (ORCPT );\n\tTue, 5 Sep 2017 14:27:17 -0400","from mail.kernel.org ([198.145.29.99]:59604 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752174AbdIES1Q (ORCPT );\n\tTue, 5 Sep 2017 14:27:16 -0400","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 30EEC21B64;\n\tTue, 5 Sep 2017 18:27:16 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 30EEC21B64","Subject":"[PATCH 3/4] PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic\n\tPCI_EXP_RTCTL offset","From":"Bjorn Helgaas ","To":"Jon Mason , Ray Jui ,\n\tOza Pawandeep , Tanmay Inamdar ,\n\tScott Branden ","Cc":"linux-pci@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com","Date":"Tue, 05 Sep 2017 13:27:14 -0500","Message-ID":"<20170905182714.27030.75573.stgit@bhelgaas-glaptop.roam.corp.google.com>","In-Reply-To":"<20170905181602.27030.65715.stgit@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170905181602.27030.65715.stgit@bhelgaas-glaptop.roam.corp.google.com>","User-Agent":"StGit/0.17.1-dirty","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"Apparently the PCIe capability is at address 0x40 in config space of X-Gene\nv1 Root Ports. Add a definition of that and use the generic PCI_EXP_RTCTL\noffset into the capability. No functional change intended.\n\nSigned-off-by: Bjorn Helgaas \n---\n drivers/pci/host/pci-xgene.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c\nindex bd897479a215..af47ebd70e22 100644\n--- a/drivers/pci/host/pci-xgene.c\n+++ b/drivers/pci/host/pci-xgene.c\n@@ -61,7 +61,7 @@\n #define SZ_1T\t\t\t\t(SZ_1G*1024ULL)\n #define PIPE_PHY_RATE_RD(src)\t\t((0xc000 & (u32)(src)) >> 0xe)\n \n-#define ROOT_CAP_AND_CTRL\t\t0x5C\n+#define XGENE_V1_PCI_EXP_CAP\t\t0x40\n \n /* PCIe IP version */\n #define XGENE_PCIE_IP_VER_UNKN\t\t0\n@@ -189,7 +189,7 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,\n \t * Avoid this by not claiming to support CRS.\n \t */\n \tif (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&\n-\t ((where & ~0x3) == ROOT_CAP_AND_CTRL))\n+\t ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))\n \t\t*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);\n \n \tif (size <= 2)\n","prefixes":["3/4"]}