{"id":810076,"url":"http://patchwork.ozlabs.org/api/patches/810076/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170905103008.3099-3-wenyou.yang@microchip.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170905103008.3099-3-wenyou.yang@microchip.com>","list_archive_url":null,"date":"2017-09-05T10:30:08","name":"[U-Boot,2/2] ARM: dts: at91: sama5: Add the sfr node","commit_ref":"56246d1e87050bf22198e95c4526331a94c8a520","pull_url":null,"state":"accepted","archived":false,"hash":"b4bf1858d82a3377ab30fbd991a4ef0dd1ad029f","submitter":{"id":69532,"url":"http://patchwork.ozlabs.org/api/people/69532/?format=json","name":"Wenyou Yang","email":"Wenyou.Yang@microchip.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170905103008.3099-3-wenyou.yang@microchip.com/mbox/","series":[{"id":1547,"url":"http://patchwork.ozlabs.org/api/series/1547/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=1547","date":"2017-09-05T10:30:06","name":"clk: at91: utmi: Fix to set the main clock","version":1,"mbox":"http://patchwork.ozlabs.org/series/1547/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810076/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810076/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmjmh0sszz9sNr\n\tfor ;\n\tTue, 5 Sep 2017 20:36:04 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid D48A2C21F2C; Tue, 5 Sep 2017 10:35:38 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id ABCDCC21FBB;\n\tTue, 5 Sep 2017 10:35:36 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 172F6C21FC6; Tue, 5 Sep 2017 10:35:11 +0000 (UTC)","from eusmtp01.atmel.com (eusmtp01.atmel.com [212.144.249.243])\n\tby lists.denx.de (Postfix) with ESMTPS id A33DEC21D8D\n\tfor ; Tue, 5 Sep 2017 10:35:07 +0000 (UTC)","from apsmtp01.atmel.com (10.168.254.31) by eusmtp01.atmel.com\n\t(10.145.145.31) with Microsoft SMTP Server id 14.3.235.1;\n\tTue, 5 Sep 2017 12:34:27 +0200","from shaarm01.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com\n\t(10.168.254.31) with Microsoft SMTP Server id 14.3.235.1;\n\tTue, 5 Sep 2017 18:38:44 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","From":"Wenyou Yang ","To":"U-Boot Mailing List ","Date":"Tue, 5 Sep 2017 18:30:08 +0800","Message-ID":"<20170905103008.3099-3-wenyou.yang@microchip.com>","X-Mailer":"git-send-email 2.13.0","In-Reply-To":"<20170905103008.3099-1-wenyou.yang@microchip.com>","References":"<20170905103008.3099-1-wenyou.yang@microchip.com>","MIME-Version":"1.0","Cc":"Tom Rini , Stephen Warren ","Subject":"[U-Boot] [PATCH 2/2] ARM: dts: at91: sama5: Add the sfr node","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"For sama5d2, add the sfr node with syscon support.\n\nIn order to access the SFR_UTMICKTRIM register for the utmi clock\ndriver, add the phandle property for the utmi node to point to the\nsfr node.\n\nSigned-off-by: Wenyou Yang \n---\n\n arch/arm/dts/sama5d2.dtsi | 6 ++++++\n arch/arm/dts/sama5d3.dtsi | 2 ++\n 2 files changed, 8 insertions(+)","diff":"diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi\nindex d8a65145d6..4233ef8c18 100644\n--- a/arch/arm/dts/sama5d2.dtsi\n+++ b/arch/arm/dts/sama5d2.dtsi\n@@ -122,6 +122,7 @@\n \t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-utmi\";\n \t\t\t\t\t#clock-cells = <0>;\n \t\t\t\t\tclocks = <&main>;\n+\t\t\t\t\tregmap-sfr = <&sfr>;\n \t\t\t\t\tu-boot,dm-pre-reloc;\n \t\t\t\t};\n \n@@ -660,6 +661,11 @@\n \t\t\t\tstatus = \"disabled\";\n \t\t\t};\n \n+\t\t\tsfr: sfr@f8030000 {\n+\t\t\t\tcompatible = \"atmel,sama5d2-sfr\", \"syscon\";\n+\t\t\t\treg = <0xf8030000 0x98>;\n+\t\t\t};\n+\n \t\t\tsckc@f8048050 {\n \t\t\t\tcompatible = \"atmel,at91sam9x5-sckc\";\n \t\t\t\treg = <0xf8048050 0x4>;\ndiff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi\nindex 84ee089202..ee0e14e516 100644\n--- a/arch/arm/dts/sama5d3.dtsi\n+++ b/arch/arm/dts/sama5d3.dtsi\n@@ -998,6 +998,8 @@\n \t\t\t\t\tinterrupt-parent = <&pmc>;\n \t\t\t\t\tinterrupts = ;\n \t\t\t\t\tclocks = <&main>;\n+\t\t\t\t\tregmap-sfr = <&sfr>;\n+\t\t\t\t\tu-boot,dm-pre-reloc;\n \t\t\t\t};\n \n \t\t\t\tmck: masterck {\n","prefixes":["U-Boot","2/2"]}