{"id":809721,"url":"http://patchwork.ozlabs.org/api/patches/809721/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504538995-13792-1-git-send-email-clombard@linux.vnet.ibm.com/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<1504538995-13792-1-git-send-email-clombard@linux.vnet.ibm.com>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/1504538995-13792-1-git-send-email-clombard@linux.vnet.ibm.com/","date":"2017-09-04T15:29:55","name":"[V2] cxl: Add support for POWER9 DD2","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"8b328ba6cba4e5f28b9061d45a97ded2e2cd3ee9","submitter":{"id":67351,"url":"http://patchwork.ozlabs.org/api/people/67351/?format=json","name":"Christophe Lombard","email":"clombard@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504538995-13792-1-git-send-email-clombard@linux.vnet.ibm.com/mbox/","series":[{"id":1406,"url":"http://patchwork.ozlabs.org/api/series/1406/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=1406","date":"2017-09-04T15:29:55","name":"[V2] cxl: Add support for POWER9 DD2","version":2,"mbox":"http://patchwork.ozlabs.org/series/1406/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809721/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809721/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmDMl4WS9z9s7C\n\tfor ;\n\tTue, 5 Sep 2017 01:31:15 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xmDMl3h16zDqrx\n\tfor ;\n\tTue, 5 Sep 2017 01:31:15 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xmDLQ1yD5zDqjv\n\tfor ;\n\tTue, 5 Sep 2017 01:30:05 +1000 (AEST)","from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv84FTDKA012858\n\tfor ; Mon, 4 Sep 2017 11:30:03 -0400","from e06smtp13.uk.ibm.com (e06smtp13.uk.ibm.com [195.75.94.109])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cs8rsjjwm-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Mon, 04 Sep 2017 11:30:03 -0400","from localhost\n\tby e06smtp13.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tMon, 4 Sep 2017 16:29:59 +0100","from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com\n\t[9.149.105.61])\n\tby b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v84FTx2C13697142; Mon, 4 Sep 2017 15:29:59 GMT","from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id DE2A111C052;\n\tMon, 4 Sep 2017 16:26:22 +0100 (BST)","from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id ED23011C04C;\n\tMon, 4 Sep 2017 16:26:21 +0100 (BST)","from lombard-w520.ibm.com (unknown [9.164.186.244])\n\tby d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tMon, 4 Sep 2017 16:26:21 +0100 (BST)"],"Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=clombard@linux.vnet.ibm.com; receiver=)","From":"Christophe Lombard ","To":"linuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,\n\tvaibhav@linux.vnet.ibm.com, andrew.donnellan@au1.ibm.com","Subject":"[PATCH V2] cxl: Add support for POWER9 DD2","Date":"Mon, 4 Sep 2017 17:29:55 +0200","X-Mailer":"git-send-email 2.7.4","X-TM-AS-GCONF":"00","x-cbid":"17090415-0012-0000-0000-0000057487A0","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17090415-0013-0000-0000-000018ECBB2D","Message-Id":"<1504538995-13792-1-git-send-email-clombard@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-04_09:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709040248","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"The PSL initialization sequence has been updated to DD2.\nThis patch adapts to the changes, retaining compatibility with DD1.\nThe patch includes some changes to DD1 fix-ups as well.\n\nTests performed on some of the old/new hardware.\n\nThe function is_page_fault(), for POWER9, lists the Translation Checkout\nResponses where the page fault will be handled by copro_handle_mm_fault().\nThis list is too restrictive and not necessary.\n\nThis patches removes this restriction and all page faults, whatever the\nreason, will be handled. In this case, the interruption is always\nacknowledged.\n\nSigned-off-by: Christophe Lombard \n\n---\nChangelog[v2]\n - Rebase to latest upstream.\n - Update the function is_page_fault()\n---\n drivers/misc/cxl/cxl.h | 2 ++\n drivers/misc/cxl/fault.c | 15 ++-------------\n drivers/misc/cxl/pci.c | 46 +++++++++++++++++++++++-----------------------\n 3 files changed, 27 insertions(+), 36 deletions(-)","diff":"diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h\nindex b1afecc..0167df8 100644\n--- a/drivers/misc/cxl/cxl.h\n+++ b/drivers/misc/cxl/cxl.h\n@@ -100,6 +100,8 @@ static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};\n static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};\n /* PSL registers - CAIA 2 */\n static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};\n+static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};\n+static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};\n static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};\n static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};\n static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};\ndiff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c\nindex 6eed7d0..0cf7f4a 100644\n--- a/drivers/misc/cxl/fault.c\n+++ b/drivers/misc/cxl/fault.c\n@@ -204,22 +204,11 @@ static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)\n \n static bool cxl_is_page_fault(struct cxl_context *ctx, u64 dsisr)\n {\n-\tu64 crs; /* Translation Checkout Response Status */\n-\n \tif ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_An_DM))\n \t\treturn true;\n \n-\tif (cxl_is_power9()) {\n-\t\tcrs = (dsisr & CXL_PSL9_DSISR_An_CO_MASK);\n-\t\tif ((crs == CXL_PSL9_DSISR_An_PF_SLR) ||\n-\t\t (crs == CXL_PSL9_DSISR_An_PF_RGC) ||\n-\t\t (crs == CXL_PSL9_DSISR_An_PF_RGP) ||\n-\t\t (crs == CXL_PSL9_DSISR_An_PF_HRH) ||\n-\t\t (crs == CXL_PSL9_DSISR_An_PF_STEG) ||\n-\t\t (crs == CXL_PSL9_DSISR_An_URTCH)) {\n-\t\t\treturn true;\n-\t\t}\n-\t}\n+\tif (cxl_is_power9())\n+\t\treturn true;\n \n \treturn false;\n }\ndiff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c\nindex d18b3d9..3edc991 100644\n--- a/drivers/misc/cxl/pci.c\n+++ b/drivers/misc/cxl/pci.c\n@@ -401,7 +401,8 @@ int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,\n \t*capp_unit_id = get_capp_unit_id(np, *phb_index);\n \tof_node_put(np);\n \tif (!*capp_unit_id) {\n-\t\tpr_err(\"cxl: invalid capp unit id\\n\");\n+\t\tpr_err(\"cxl: invalid capp unit id (phb_index: %d)\\n\",\n+\t\t *phb_index);\n \t\treturn -ENODEV;\n \t}\n \n@@ -475,37 +476,36 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,\n \tpsl_fircntl |= 0x1ULL; /* ce_thresh */\n \tcxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);\n \n-\t/* vccredits=0x1 pcklat=0x4 */\n-\tcxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);\n-\n-\t/*\n-\t * For debugging with trace arrays.\n-\t * Configure RX trace 0 segmented mode.\n-\t * Configure CT trace 0 segmented mode.\n-\t * Configure LA0 trace 0 segmented mode.\n-\t * Configure LA1 trace 0 segmented mode.\n+\t/* Setup the PSL to transmit packets on the PCIe before the\n+\t * CAPP is enabled\n \t */\n-\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);\n-\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);\n-\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);\n-\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);\n+\tcxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000002A10ULL);\n \n \t/*\n \t * A response to an ASB_Notify request is returned by the\n \t * system as an MMIO write to the address defined in\n-\t * the PSL_TNR_ADDR register\n+\t * the PSL_TNR_ADDR register.\n+\t * keep the Reset Value: 0x00020000E0000000\n \t */\n-\t/* PSL_TNR_ADDR */\n \n-\t/* NORST */\n-\tcxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);\n+\t/* Enable XSL rty limit */\n+\tcxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);\n+\n+\t/* Change XSL_INV dummy read threshold */\n+\tcxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);\n \n-\t/* allocate the apc machines */\n-\tcxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);\n+\tif (phb_index == 3) {\n+\t\t/* disable machines 31-47 and 20-27 for DMA */\n+\t\tcxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);\n+\t}\n+\n+\t/* Snoop machines */\n+\tcxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);\n \n-\t/* Disable vc dd1 fix */\n-\tif (cxl_is_power9_dd1())\n-\t\tcxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);\n+\tif (cxl_is_power9_dd1()) {\n+\t\t/* Disabling deadlock counter CAR */\n+\t\tcxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);\n+\t}\n \n \treturn 0;\n }\n","prefixes":["V2"]}