{"id":809672,"url":"http://patchwork.ozlabs.org/api/patches/809672/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-36-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-36-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:26:06","name":"[PULL,35/36] target/arm: Fix aa64 ldp register writeback","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e44bf1d39d4f6fd1c8e072e9e3d81deca9182277","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-36-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809672/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809672/checks/","tags":{},"related":[],"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm92727T0z9t2c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon,  4 Sep 2017 23:00:47 +1000 (AEST)","from localhost ([::1]:60593 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1doqzd-0006wC-Bt\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 09:00:45 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52954)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSk-0005Fo-8L\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:54 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSX-00050p-0s\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:46 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37140)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1doqSW-000503-Qa\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:32 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>) id 1doqSV-0005eU-RS\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:31 +0100"],"From":"Peter Maydell <peter.maydell@linaro.org>","To":"qemu-devel@nongnu.org","Date":"Mon,  4 Sep 2017 13:26:06 +0100","Message-Id":"<1504527967-29248-36-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 35/36] target/arm: Fix aa64 ldp register\n\twriteback","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"<qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<http://lists.nongnu.org/archive/html/qemu-devel/>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"},"content":"From: Richard Henderson <richard.henderson@linaro.org>\n\nFor \"ldp x0, x1, [x0]\", if the second load is on a second page and\nthe second page is unmapped, the exception would be raised with x0\nalready modified.  This means the instruction couldn't be restarted.\n\nCc: qemu-arm@nongnu.org\nCc: qemu-stable@nongnu.org\nReported-by: Andrew <andrew@fubar.geek.nz>\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-id: 20170825224833.4463-1-richard.henderson@linaro.org\nFixes: https://bugs.launchpad.net/qemu/+bug/1713066\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n[PMM: tweaked comment format]\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/translate-a64.c | 29 +++++++++++++++++------------\n 1 file changed, 17 insertions(+), 12 deletions(-)","diff":"diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex 2200e25..cb44632 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -2217,29 +2217,34 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)\n         } else {\n             do_fp_st(s, rt, tcg_addr, size);\n         }\n-    } else {\n-        TCGv_i64 tcg_rt = cpu_reg(s, rt);\n-        if (is_load) {\n-            do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,\n-                      false, 0, false, false);\n-        } else {\n-            do_gpr_st(s, tcg_rt, tcg_addr, size,\n-                      false, 0, false, false);\n-        }\n-    }\n-    tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);\n-    if (is_vector) {\n+        tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);\n         if (is_load) {\n             do_fp_ld(s, rt2, tcg_addr, size);\n         } else {\n             do_fp_st(s, rt2, tcg_addr, size);\n         }\n     } else {\n+        TCGv_i64 tcg_rt = cpu_reg(s, rt);\n         TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);\n+\n         if (is_load) {\n+            TCGv_i64 tmp = tcg_temp_new_i64();\n+\n+            /* Do not modify tcg_rt before recognizing any exception\n+             * from the second load.\n+             */\n+            do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false,\n+                      false, 0, false, false);\n+            tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);\n             do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false,\n                       false, 0, false, false);\n+\n+            tcg_gen_mov_i64(tcg_rt, tmp);\n+            tcg_temp_free_i64(tmp);\n         } else {\n+            do_gpr_st(s, tcg_rt, tcg_addr, size,\n+                      false, 0, false, false);\n+            tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);\n             do_gpr_st(s, tcg_rt2, tcg_addr, size,\n                       false, 0, false, false);\n         }\n","prefixes":["PULL","35/36"]}