{"id":809665,"url":"http://patchwork.ozlabs.org/api/patches/809665/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-32-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-32-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:26:02","name":"[PULL,31/36] target/arm: Allow deliver_fault() caller to specify EA bit","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fee195a671f8173d57a67dafb6b909c5021bece0","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-32-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809665/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809665/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8vG4DVWz9sNr\n\tfor ;\n\tMon, 4 Sep 2017 22:54:50 +1000 (AEST)","from localhost ([::1]:59675 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqts-0001Sr-MW\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:54:48 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52882)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSh-0005Da-3s\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:52 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqSU-0004xg-6N\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:43 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37136)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqST-0004xA-VI\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:30 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqSS-0005cg-UN\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:28 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:26:02 +0100","Message-Id":"<1504527967-29248-32-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 31/36] target/arm: Allow deliver_fault() caller\n\tto specify EA bit","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"For external aborts, we will want to be able to specify the EA\n(external abort type) bit in the syndrome field. Allow callers of\ndeliver_fault() to do that by adding a field to ARMMMUFaultInfo which\nwe use when constructing the syndrome values.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Richard Henderson \nReviewed-by: Edgar E. Iglesias \n---\n target/arm/internals.h | 2 ++\n target/arm/op_helper.c | 10 +++++-----\n 2 files changed, 7 insertions(+), 5 deletions(-)","diff":"diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex bb06946..461f558 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -448,12 +448,14 @@ void arm_handle_psci_call(ARMCPU *cpu);\n * @s2addr: Address that caused a fault at stage 2\n * @stage2: True if we faulted at stage 2\n * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk\n+ * @ea: True if we should set the EA (external abort type) bit in syndrome\n */\n typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;\n struct ARMMMUFaultInfo {\n target_ulong s2addr;\n bool stage2;\n bool s1ptw;\n+ bool ea;\n };\n \n /* Do a page table walk and add page to TLB if possible */\ndiff --git a/target/arm/op_helper.c b/target/arm/op_helper.c\nindex 6114597..8f6db80 100644\n--- a/target/arm/op_helper.c\n+++ b/target/arm/op_helper.c\n@@ -80,7 +80,7 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,\n \n static inline uint32_t merge_syn_data_abort(uint32_t template_syn,\n unsigned int target_el,\n- bool same_el,\n+ bool same_el, bool ea,\n bool s1ptw, bool is_write,\n int fsc)\n {\n@@ -99,7 +99,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,\n */\n if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {\n syn = syn_data_abort_no_iss(same_el,\n- 0, 0, s1ptw, is_write, fsc);\n+ ea, 0, s1ptw, is_write, fsc);\n } else {\n /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template\n * syndrome created at translation time.\n@@ -107,7 +107,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,\n */\n syn = syn_data_abort_with_iss(same_el,\n 0, 0, 0, 0, 0,\n- 0, 0, s1ptw, is_write, fsc,\n+ ea, 0, s1ptw, is_write, fsc,\n false);\n /* Merge the runtime syndrome with the template syndrome. */\n syn |= template_syn;\n@@ -141,11 +141,11 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,\n }\n \n if (access_type == MMU_INST_FETCH) {\n- syn = syn_insn_abort(same_el, 0, fi->s1ptw, fsc);\n+ syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);\n exc = EXCP_PREFETCH_ABORT;\n } else {\n syn = merge_syn_data_abort(env->exception.syndrome, target_el,\n- same_el, fi->s1ptw,\n+ same_el, fi->ea, fi->s1ptw,\n access_type == MMU_DATA_STORE,\n fsc);\n if (access_type == MMU_DATA_STORE\n","prefixes":["PULL","31/36"]}