{"id":809659,"url":"http://patchwork.ozlabs.org/api/patches/809659/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-27-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-27-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:25:57","name":"[PULL,26/36] cpu: Define new cpu_transaction_failed() hook","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"712184ccda7525875b9dba34080fdfb6e2ec6736","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-27-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809659/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809659/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8qJ03Mhz9s75\n\tfor ;\n\tMon, 4 Sep 2017 22:51:24 +1000 (AEST)","from localhost ([::1]:59661 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqqY-00079x-2I\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:51:22 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52817)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSd-0005BG-Lp\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:50 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqSP-0004uj-5C\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:39 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37130)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqSO-0004tI-Sz\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:25 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqSN-0005aT-Uw\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:23 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:25:57 +0100","Message-Id":"<1504527967-29248-27-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 26/36] cpu: Define new cpu_transaction_failed()\n\thook","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Currently we have a rather half-baked setup for allowing CPUs to\ngenerate exceptions on accesses to invalid memory: the CPU has a\ncpu_unassigned_access() hook which the memory system calls in\nunassigned_mem_write() and unassigned_mem_read() if the current_cpu\npointer is non-NULL. This was originally designed before we\nimplemented the MemTxResult type that allows memory operations to\nreport a success or failure code, which is why the hook is called\nright at the bottom of the memory system. The major problem with\nthis is that it means that the hook can be called even when the\naccess was not actually done by the CPU: for instance if the CPU\nwrites to a DMA engine register which causes the DMA engine to begin\na transaction which has been set up by the guest to operate on\ninvalid memory then this will casue the CPU to take an exception\nincorrectly. Another minor problem is that currently if a device\nreturns a transaction error then this won't turn into a CPU exception\nat all.\n\nThe right way to do this is to have allow the CPU to respond\nto memory system transaction failures at the point where the\nCPU specific code calls into the memory system.\n\nDefine a new QOM CPU method and utility function\ncpu_transaction_failed() which is called in these cases.\nThe functionality here overlaps with the existing\ncpu_unassigned_access() because individual target CPUs will\nneed some work to convert them to the new system. When this\ntransition is complete we can remove the old cpu_unassigned_access()\ncode.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Richard Henderson \nReviewed-by: Edgar E. Iglesias \n---\n include/qom/cpu.h | 22 ++++++++++++++++++++++\n 1 file changed, 22 insertions(+)","diff":"diff --git a/include/qom/cpu.h b/include/qom/cpu.h\nindex b7ac949..08bd868 100644\n--- a/include/qom/cpu.h\n+++ b/include/qom/cpu.h\n@@ -85,8 +85,11 @@ struct TranslationBlock;\n * @has_work: Callback for checking if there is work to do.\n * @do_interrupt: Callback for interrupt handling.\n * @do_unassigned_access: Callback for unassigned access handling.\n+ * (this is deprecated: new targets should use do_transaction_failed instead)\n * @do_unaligned_access: Callback for unaligned access handling, if\n * the target defines #ALIGNED_ONLY.\n+ * @do_transaction_failed: Callback for handling failed memory transactions\n+ * (ie bus faults or external aborts; not MMU faults)\n * @virtio_is_big_endian: Callback to return %true if a CPU which supports\n * runtime configurable endianness is currently big-endian. Non-configurable\n * CPUs can use the default implementation of this method. This method should\n@@ -153,6 +156,10 @@ typedef struct CPUClass {\n void (*do_unaligned_access)(CPUState *cpu, vaddr addr,\n MMUAccessType access_type,\n int mmu_idx, uintptr_t retaddr);\n+ void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,\n+ unsigned size, MMUAccessType access_type,\n+ int mmu_idx, MemTxAttrs attrs,\n+ MemTxResult response, uintptr_t retaddr);\n bool (*virtio_is_big_endian)(CPUState *cpu);\n int (*memory_rw_debug)(CPUState *cpu, vaddr addr,\n uint8_t *buf, int len, bool is_write);\n@@ -847,6 +854,21 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,\n \n cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);\n }\n+\n+static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,\n+ vaddr addr, unsigned size,\n+ MMUAccessType access_type,\n+ int mmu_idx, MemTxAttrs attrs,\n+ MemTxResult response,\n+ uintptr_t retaddr)\n+{\n+ CPUClass *cc = CPU_GET_CLASS(cpu);\n+\n+ if (cc->do_transaction_failed) {\n+ cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,\n+ mmu_idx, attrs, response, retaddr);\n+ }\n+}\n #endif\n \n #endif /* NEED_CPU_H */\n","prefixes":["PULL","26/36"]}