{"id":809657,"url":"http://patchwork.ozlabs.org/api/patches/809657/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-31-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-31-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:26:01","name":"[PULL,30/36] target/arm: Factor out fault delivery code","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b3cf449415542bce44165a283d873da37109cc97","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-31-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809657/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809657/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8mj1lP3z9sNr\n\tfor ;\n\tMon, 4 Sep 2017 22:49:09 +1000 (AEST)","from localhost ([::1]:59652 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqoN-0005BS-7b\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:49:07 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52894)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSh-0005Dc-Dx\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:53 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqST-0004xP-OB\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:43 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37134)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqST-0004wD-F0\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:29 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqSS-0005c3-2v\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:28 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:26:01 +0100","Message-Id":"<1504527967-29248-31-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 30/36] target/arm: Factor out fault delivery code","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"We currently have some similar code in tlb_fill() and in\narm_cpu_do_unaligned_access() for delivering a data abort or prefetch\nabort. We're also going to want to do the same thing to handle\nexternal aborts. Factor out the common code into a new function\ndeliver_fault().\n\nSigned-off-by: Peter Maydell \nReviewed-by: Richard Henderson \nAcked-by: Edgar E. Iglesias \n---\n target/arm/op_helper.c | 110 +++++++++++++++++++++++++------------------------\n 1 file changed, 57 insertions(+), 53 deletions(-)","diff":"diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c\nindex 5a94a5f..6114597 100644\n--- a/target/arm/op_helper.c\n+++ b/target/arm/op_helper.c\n@@ -115,6 +115,51 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,\n return syn;\n }\n \n+static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,\n+ uint32_t fsr, uint32_t fsc, ARMMMUFaultInfo *fi)\n+{\n+ CPUARMState *env = &cpu->env;\n+ int target_el;\n+ bool same_el;\n+ uint32_t syn, exc;\n+\n+ target_el = exception_target_el(env);\n+ if (fi->stage2) {\n+ target_el = 2;\n+ env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;\n+ }\n+ same_el = (arm_current_el(env) == target_el);\n+\n+ if (fsc == 0x3f) {\n+ /* Caller doesn't have a long-format fault status code. This\n+ * should only happen if this fault will never actually be reported\n+ * to an EL that uses a syndrome register. Check that here.\n+ * 0x3f is a (currently) reserved FSC code, in case the constructed\n+ * syndrome does leak into the guest somehow.\n+ */\n+ assert(target_el != 2 && !arm_el_is_aa64(env, target_el));\n+ }\n+\n+ if (access_type == MMU_INST_FETCH) {\n+ syn = syn_insn_abort(same_el, 0, fi->s1ptw, fsc);\n+ exc = EXCP_PREFETCH_ABORT;\n+ } else {\n+ syn = merge_syn_data_abort(env->exception.syndrome, target_el,\n+ same_el, fi->s1ptw,\n+ access_type == MMU_DATA_STORE,\n+ fsc);\n+ if (access_type == MMU_DATA_STORE\n+ && arm_feature(env, ARM_FEATURE_V6)) {\n+ fsr |= (1 << 11);\n+ }\n+ exc = EXCP_DATA_ABORT;\n+ }\n+\n+ env->exception.vaddress = addr;\n+ env->exception.fsr = fsr;\n+ raise_exception(env, exc, syn, target_el);\n+}\n+\n /* try to fill the TLB and return an exception if error. If retaddr is\n * NULL, it means that the function was called in C code (i.e. not\n * from generated code or from helper.c)\n@@ -129,23 +174,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,\n ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fsr, &fi);\n if (unlikely(ret)) {\n ARMCPU *cpu = ARM_CPU(cs);\n- CPUARMState *env = &cpu->env;\n- uint32_t syn, exc, fsc;\n- unsigned int target_el;\n- bool same_el;\n+ uint32_t fsc;\n \n if (retaddr) {\n /* now we have a real cpu fault */\n cpu_restore_state(cs, retaddr);\n }\n \n- target_el = exception_target_el(env);\n- if (fi.stage2) {\n- target_el = 2;\n- env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;\n- }\n- same_el = arm_current_el(env) == target_el;\n-\n if (fsr & (1 << 9)) {\n /* LPAE format fault status register : bottom 6 bits are\n * status code in the same form as needed for syndrome\n@@ -153,34 +188,15 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,\n fsc = extract32(fsr, 0, 6);\n } else {\n /* Short format FSR : this fault will never actually be reported\n- * to an EL that uses a syndrome register. Check that here,\n- * and use a (currently) reserved FSR code in case the constructed\n- * syndrome does leak into the guest somehow.\n+ * to an EL that uses a syndrome register. Use a (currently)\n+ * reserved FSR code in case the constructed syndrome does leak\n+ * into the guest somehow. deliver_fault will assert that\n+ * we don't target an EL using the syndrome.\n */\n- assert(target_el != 2 && !arm_el_is_aa64(env, target_el));\n fsc = 0x3f;\n }\n \n- /* For insn and data aborts we assume there is no instruction syndrome\n- * information; this is always true for exceptions reported to EL1.\n- */\n- if (access_type == MMU_INST_FETCH) {\n- syn = syn_insn_abort(same_el, 0, fi.s1ptw, fsc);\n- exc = EXCP_PREFETCH_ABORT;\n- } else {\n- syn = merge_syn_data_abort(env->exception.syndrome, target_el,\n- same_el, fi.s1ptw,\n- access_type == MMU_DATA_STORE, fsc);\n- if (access_type == MMU_DATA_STORE\n- && arm_feature(env, ARM_FEATURE_V6)) {\n- fsr |= (1 << 11);\n- }\n- exc = EXCP_DATA_ABORT;\n- }\n-\n- env->exception.vaddress = addr;\n- env->exception.fsr = fsr;\n- raise_exception(env, exc, syn, target_el);\n+ deliver_fault(cpu, addr, access_type, fsr, fsc, &fi);\n }\n }\n \n@@ -191,9 +207,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,\n {\n ARMCPU *cpu = ARM_CPU(cs);\n CPUARMState *env = &cpu->env;\n- int target_el;\n- bool same_el;\n- uint32_t syn;\n+ uint32_t fsr, fsc;\n+ ARMMMUFaultInfo fi = {};\n ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);\n \n if (retaddr) {\n@@ -201,28 +216,17 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,\n cpu_restore_state(cs, retaddr);\n }\n \n- target_el = exception_target_el(env);\n- same_el = (arm_current_el(env) == target_el);\n-\n- env->exception.vaddress = vaddr;\n-\n /* the DFSR for an alignment fault depends on whether we're using\n * the LPAE long descriptor format, or the short descriptor format\n */\n if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {\n- env->exception.fsr = (1 << 9) | 0x21;\n+ fsr = (1 << 9) | 0x21;\n } else {\n- env->exception.fsr = 0x1;\n- }\n-\n- if (access_type == MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) {\n- env->exception.fsr |= (1 << 11);\n+ fsr = 0x1;\n }\n+ fsc = 0x21;\n \n- syn = merge_syn_data_abort(env->exception.syndrome, target_el,\n- same_el, 0, access_type == MMU_DATA_STORE,\n- 0x21);\n- raise_exception(env, EXCP_DATA_ABORT, syn, target_el);\n+ deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi);\n }\n \n #endif /* !defined(CONFIG_USER_ONLY) */\n","prefixes":["PULL","30/36"]}